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High Speed Data Converters /
High speed data converters represent one of the most challenging, important and exciting analog and mixed-signal systems. They are ubiquitous in our modern and highly connected world. Understanding and designing this class of converters require proficiency in analog circuit design, digital design, a...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London, United Kingdom :
Institution of Engineering and Technology,
2016.
|
| Colección: | Materials, circuits and devices series ;
26. |
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Machine generated contents note: 1. Introduction
- 1.1. Ideal data conversion
- 1.2. The sampling operation
- 1.2.1. Sampling theorem
- 1.2.2. Sampling of bandpass signals
- 1.3. The reconstruction operation
- 1.4. The quantization operation
- 1.5. Coding
- 1.6. Undersampling and oversampling
- 1.7. Decimation and interpolation
- 1.8. Conclusion
- Problems
- References
- 2. Performance metrics
- 2.1. Resolution and sampling rate
- 2.2. Signal-to-noise-and-distortion ratio (SNDR or SINAD)
- 2.3. Spurious-free dynamic range (SFDR)
- 2.3.1. HD2 and HD3
- 2.3.2. Differential operation
- 2.4. Inter-modulation distortion (IMD)
- 2.5. Relationship between HD and IMD
- 2.6. Differential and integral non-linearity (DNL and INL)
- 2.7. Relationship between SFDR and INL
- 2.7.1. HD2 and HD3 INL patterns
- 2.7.2. Saw-tooth INL pattern
- 2.8. Offset and gain error
- 2.9. Jitter
- 2.9.1. Analysis
- 2.9.2. Intuitive perspective
- 2.9.3. Jitter measurement
- 2.9.4. Types of random jitter.
- Note continued: 2.9.5. Jitter and phase noise
- 2.10. Bit error rate (BER)
- 2.11. Power consumption and figure of merit
- 2.12. Conclusion
- Problems
- References
- 3. Data converter architectures
- 3.1. Flash ADC
- 3.2. Flash ADC with interpolation
- 3.3. Multi-step ADC
- 3.4. Sub-ranging ADC
- 3.5. Folding ADC
- 3.6. Pipelined ADC
- 3.7. Successive approximation (SAR) ADC
- 3.8. Pipelined and SAR ADC
- 3.9. Time-interleaved ADC
- 3.10. Sigma-delta ADC
- 3.10.1. Oversampling and noise shaping
- 3.10.2. Single-bit modulator
- 3.10.3. Overloading
- 3.10.4. First-order modulator
- 3.10.5. Second-order modulator
- 3.10.6. Higher order and cascaded sigma-delta modulators
- 3.10.7. Discrete-time and continuous-time sigma-delta modulators
- 3.10.8. Multi-bit modulator
- 3.10.9. Bandpass Sigma-delta converter
- 3.10.10. Concluding remarks
- 3.11. DAC architectures
- 3.11.1. Resistive DAC
- 3.11.2. Capacitive DAC
- 3.11.3. Current steering DAC
- 3.12. Conclusion
- Problems.
- Note continued: References
- 4. Sampling
- 4.1. CMOS samplers
- 4.1.1. Sampling noise
- 4.1.2. Sampling linearity
- 4.2. Input buffer
- 4.2.1. Input buffer design
- 4.2.2. Input buffer non-linearity
- 4.2.3. Summary of trade-offs
- 4.3.Complementary bipolar sample and hold
- 4.4. Clock jitter
- 4.5. Conclusion
- Problems
- References
- 5.Comparators
- 5.1.Comparator function
- 5.2.Comparator structure
- 5.2.1. Open loop comparator
- 5.2.2.Comparators with hysteresis
- 5.2.3. Regenerative comparators
- 5.3. Metastability
- 5.4. Switched capacitor comparators
- 5.4.1. Level shifting input network
- 5.4.2. Charge redistribution input network
- 5.5. Offset cancellation
- 5.6. Loading and kick-back
- 5.7.Comparator examples
- 5.8. Conclusion
- Problems
- References
- 6. Amplifiers
- 6.1. Switched capacitor circuits
- 6.1.1. Switched capacitor resistor
- 6.1.2. Switched capacitor active filters
- 6.1.3. Switched capacitor amplifiers.
- Note continued: 6.1.4. Non-idealities of a switch capacitor amplifier
- 6.2. Amplifier design
- 6.2.1. DC gain
- 6.2.2. Slew rate
- 6.2.3. Small-signal settling
- 6.2.4. CMRR and PSRR
- 6.2.5. Noise
- 6.3. Operational amplifiers
- 6.3.1. The differential pair
- 6.3.2. The Miller effect
- 6.3.3. The cascode amplifier
- 6.3.4. The active cascode amplifier
- 6.3.5. The two-stage amplifier
- 6.3.6. The common-mode feedback
- 6.4. Conclusion
- Problems
- References
- 7. Pipelined A/D converters
- 7.1. Architecture
- 7.2. Switched capacitor MDACs
- 7.2.1. Reference buffer
- 7.3. Performance limitations
- 7.3.1. Sampling non-linearity
- 7.3.2. Quantization non-linearity
- 7.3.3. Noise and jitter
- 7.4. Pipelined ADC design considerations
- 7.4.1. Sampling capacitance value and input full-scale
- 7.4.2. Number of bits per stage
- 7.4.3. Scaling factor
- 7.4.4. Input buffer
- 7.5. Accuracy and speed challenge
- 7.6. Conclusion
- Problems
- References.
- Note continued: 8. Time-interleaved converters
- 8.1. Time-interleaving
- 8.2. Offset mismatch
- 8.2.1. Special cases
- 8.2.2. Intuitive perspective
- 8.3. Gain mismatch
- 8.3.1. Special cases
- 8.3.2. Intuitive perspective
- 8.4. Timing mismatch
- 8.4.1. Special cases
- 8.4.2. Intuitive perspective
- 8.5. Bandwidth mismatch
- 8.6. Mismatch summary
- 8.7. Ping-pong special cases
- 8.7.1.M = 2, gain mismatch only
- 8.7.2.M = 2, phase mismatch only
- 8.8. Non-linearity mismatch
- 8.9. Improving performance
- 8.9.1. Improving matching
- 8.9.2. Using a full-speed sample and hold
- 8.9.3. Calibration
- 8.9.4. Randomization
- 8.10. Conclusion
- Problems
- References
- 9. Digitally assisted converters
- 9.1. Calibration of pipelined ADC non-linearity
- 9.1.1. Factory and foreground calibration
- 9.1.2. Correlation-based calibration
- 9.1.3. Summing node calibration
- 9.1.4. Reference ADC calibration
- 9.1.5. Split-ADC calibration
- 9.1.6. Settling error calibration.
- Note continued: 9.1.7. Memory calibration
- 9.1.8. Kick-back calibration
- 9.1.9. Residue amplifier non-linearity
- 9.1.10. Coupling calibration
- 9.2. Dither
- 9.3. Flash sub-ADC calibration
- 9.4. Calibration of mismatches in interleaved ADCs
- 9.4.1. Offset mismatch calibration
- 9.4.2. Gain mismatch calibration
- 9.4.3. Timing mismatch calibration
- 9.4.4. Other mismatches
- 9.4.5. Randomization
- 9.5. Conclusion
- Problems
- References
- 10. Evolution and trends
- 10.1. Performance evolution
- 10.2. Process evolution
- 10.3. Future trends
- References.