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HDL with digital design : VHDL and Verilog /
This book introduces the latest version of hardware description languages and explains how the languages can be implemented in the design of the digital logic components. In addition to digital design, other examples in the areas of bioengineering and basic computer design are covered. It introduces...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dulles, Virginia :
Mercury Learning and Information,
[2015]
|
| Colección: | Engineering series.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 082 | 0 | 4 | |a 621.39/2 |2 23 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Botros, Nazeih, |d 1945- |e author. | |
| 245 | 1 | 0 | |a HDL with digital design : |b VHDL and Verilog / |c Nazeih Botros. |
| 246 | 3 | |a Hardware description language with digital design : |b Very High Speed Integrated Circuit Hardware Description Language and Verilog | |
| 264 | 1 | |a Dulles, Virginia : |b Mercury Learning and Information, |c [2015] | |
| 300 | |a 1 online resource (xiv, 564 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file | ||
| 347 | |b PDF | ||
| 490 | 1 | |a Engineering series | |
| 500 | |a Includes index. | ||
| 588 | 0 | |a Print version record. | |
| 520 | |a This book introduces the latest version of hardware description languages and explains how the languages can be implemented in the design of the digital logic components. In addition to digital design, other examples in the areas of bioengineering and basic computer design are covered. It introduces mixed language programming by covering both Verilog and VHDL side by side. Students, as well as professionals, can learn both the theoretical and practical concepts of digital design. The two languages are equally important in the field of computer engineering and computer science as well as other engineering fields such as simulation and modeling. This resource uses the latest versions of both Verilog and VHDL; includes fundamentals of synthesis and FPGAs implementation; instructor's resources available upon adoption. -- |c Edited summary from book. | ||
| 505 | 0 | 0 | |g Introduction -- |t Hardware description languages -- |t Structure of the HDL module -- |t Structure of Verilog Module -- |t Stles (types) of description -- |t Data flow description -- |t Behavioral description -- |t Structural description -- |t Switch-level description -- |t Mixed-type description -- |t Mixed-languages description -- |t Ports -- |t VHDL ports -- |t Verilog ports -- |t Operators -- |t Logical operators -- |t VHDL logical operators -- |t Verilog logical operators -- |t Relational Operators -- |t VHD Relational Operators -- |t Verilog Relational Operators -- |t Arithmetic Operators -- |t VHD Arithmeti Operators -- |t Verilog Arithmeti Operators -- |t Arithmetic operator precedence -- |t Shift and rotate operators -- |t VHDL shift/rotate operators -- |t Verilog shift operators -- |t Date types -- |t VHDL Data types -- |t Scalar types -- |t Composite types -- |t Access types -- |t File types -- |t Other types -- |t Verilog data types -- |t Nets -- |t Register -- |t Vectors -- |t Integers -- |t Real -- |t Parameter -- |t Arrays -- |t Simulation and synthesis -- |t Brief comparison of VHDL and verilog -- |t Summary -- |t Exercises -- |g Chapter 2 |t Data-flow description -- |t Highlights of data-flow description -- |t Signal declaration and assignment statement -- |t Constant declaration and constant assignment statements -- |t Assigning a delay time to the signal-assignment -- |t Data type: Vector -- |t Common programming errors -- |t Common VHDL programming errors vCommon verilog programming errors -- |g Chapter 3 |t Behavioral description -- |t Behavioral description highlights -- |t Structure of the HDL behavioral description -- |t The VHDL variable-assignment statement -- |t Sequential statements -- |t IF statement -- |t Analysis of VHDL code in listings 3.2 and 3.3 -- |t Case statement -- |t Verilog casex and casez -- |t The wait-for statement -- |t Loop statement -- |t For-loop -- |t While -loop -- |t Verilog repeat -- |t Verilog forever -- |t VHDL next and exit |g Chapter 4 |t Structural description -- |t Highlights of structural description -- |t Organization of structural description -- |t Binding -- |t State machines -- |t generate(HDL, generic (VHDL) and parameter (verilog) -- |g Switch-level description -- |t Highlights of switch-level description -- |t Useful definitions -- |t Single NMOS and PMOS switches -- |t Verilog description of NMOS and PMOS switches -- |t Verilog description of NMOS and PMOS switches -- |t Procedure, tasks, and functions -- |t MIxed-type description -- |t Advanced HDL description -- |t Synthesis basics. |
| 504 | |a Includes bibliographical references at the end of each chapters and index. | ||
| 546 | |a English. | ||
| 590 | |a Knovel |b ACADEMIC - Software Engineering | ||
| 650 | 0 | |a Computer hardware description languages. | |
| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | |a Integrated circuits |x Design and construction |x Data processing. | |
| 650 | 6 | |a Langages de description de matériel informatique. | |
| 650 | 6 | |a VHDL (Langage de description de matériel informatique) | |
| 650 | 6 | |a Verilog (Langage de description de matériel informatique) | |
| 650 | 7 | |a Computer hardware description languages |2 fast | |
| 650 | 7 | |a Integrated circuits |x Design and construction |x Data processing |2 fast | |
| 650 | 7 | |a Verilog (Computer hardware description language) |2 fast | |
| 650 | 7 | |a VHDL (Computer hardware description language) |2 fast | |
| 776 | 0 | 8 | |i Electronic reproduction of (manifestation): |a Botros, Nazeih, 1945- |t HDL with digital design. |d Dulles, Virginia : Mercury Learning and Information, [2015] |z 1938549813 |w (OCoLC)908628126 |
| 830 | 0 | |a Engineering series. | |
| 856 | 4 | 0 | |u https://appknovel.uam.elogim.com/kn/resources/kpHDLDD009/toc |z Texto completo |
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| 938 | |a Baker and Taylor |b BTCP |n BK0013897322 | ||
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