Cargando…
Handbook of thin film deposition : techniques, processes, and technologies /
The Handbook of Thin Film Deposition is a comprehensive reference focusing on thin film technologies and applications used in the semiconductor industry and the closely related areas of thin film deposition, thin film micro properties, photovoltaic solar energy applications, new materials for memory...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Waltham [Mass.] :
William Andrew,
2012.
|
| Edición: | 3rd ed. |
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Front Cover; Handbook of Thin Film Deposition; Copyright Page; Contents; Foreword; Preface; Acknowledgments; About the Editor; List of Contributors; SCALING; Introduction to Chapter 1; 1 A Perspective on Today's Scaling Challenges and Possible Future Directions; 1.1 Introduction; 1.2 Review and Update of Generalized Scaling; 1.3 Energy/Performance Considerations; 1.4 Design Issues with Back-Gated Thin SOI CMOS; 1.5 Carrier Confinement and Quantization Effects; 1.6 Potential of Low-Temperature Operation; 1.7 Conclusion; Acknowledgments; References.
- 2 Scaling and Its Implications for the Integration and Design of Thin Film and Processes2.1 Scaling: Basics, Causes, and Consequences; 2.1.1 Moore's Law; 2.1.2 Dennard's Scaling Theory; 2.1.3 Causes and Consequences of Scaling; Causes; Consequences; Gate Oxide and Vertical Scaling; 2.1.4 Challenges and Limiters; 2.2 FEOL Scaling: State of the Art Transistors Described in Refs [51,52]; 2.2.1 Role of Lithography; 2.2.2 The Design Cycle: How Scaling Is Implemented; Migration to a New Process; Logic Characterization Phase; Design Phase; 2.2.3 Going Beyond FEOL Scaling Limits; Gate Scaling.
- Strain Engineering for Enhancing MobilityLeakage Issues; Transistor Parameters: Vt, Tox, and L: Why Does Leakage and Power Consumed per Transistor Increase with Scaling?; 2.3 Silicon on Insulator and System on a Chip; 2.3.1 Silicon Substrate and Scaling; Silicon and Silicon Oxide; 2.3.2 Necessity and Advantages of SOI; SOI References; Advantages of SOI-DRAM; Advantages of SOI for Microprocessors; New Material: Graphine FET; Strained SOI; 2.4 Back End of the Line Scaling; 2.4.1 Limiters to Back-End Scaling; 2.4.2 Change to Cu-Low K; Input-Output, IO, Scaling-Rent's Rule [35]
- Technology Nodes and Wiring Layers2.5 International Technology Roadmap for Semiconductors, See Ref. [65]; 2.6 Miscellaneous Effects; 2.6.1 Scaling and Contamination; 2.6.2 IO Scaling: Pb-Free Initiative [47]; 2.6.3 Materials Changes and Challenges; 2.6.4 IBM 7 C4 Pb Bump Process; 2.6.5 New Materials and Memory Scaling; 2.7 Scaling and Reliability [38,40,63]; 2.7.1 Technology Scaling and Wiring Layers; 2.8 Economics of Scaling; 2.9 Summary and Conclusions; Acknowledgments; References; Appendix 1: Basis for Scaling: Shannon's Theorem; Appendix 2: Rent's Rule and Consequences for Scaling.
- Appendix 3: Comparison of Changes and New Materials Going from Micro- to NanotransistorsAppendix 4: Summary of Back-End Changes in Materials and Processing; Appendix 5: List of Abbreviations; 3 Scaling-Its Effects on Heat Generation and Cooling of Devices. A "Thermal Moore's" Law?; 3.1 Purpose of This Section; 3.2 Heat Generation Trends from Chips; 3.3 The Chip-Cooling Problem and Its Importance; 3.4 Definition of TDP, Thermal Resistance, TDD Versus SPECINT; and Their Use [4]; 3.5 Where Is the Need for Cooling?; 3.5.1 Heat Dissipation When Power Is Off; 3.5.2 Conclusions.