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Computer architecture : a quantitative approach /
'Computer Architecture: A Quantitative Approach', Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book became a part of Intel's 2012 recommended reading lis...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann/Elsevier,
©2012.
|
| Edición: | Fifth edition. |
| Colección: | The Morgan Kaufmann series in computer architecture and design
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Hennessy, John L., |e author. | |
| 245 | 1 | 0 | |a Computer architecture : |b a quantitative approach / |c John L. Hennessy, David A. Patterson ; with contributions by Krste Asanović [and others]. |
| 250 | |a Fifth edition. | ||
| 260 | |a Amsterdam ; |a Boston : |b Morgan Kaufmann/Elsevier, |c ©2012. | ||
| 300 | |a 1 online resource (xxviii, 493, [325] pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 0 | |a The Morgan Kaufmann series in computer architecture and design | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Front cover -- In praise of Computer Architecture : A Quantitative Approach Fifth Edition -- Computer Architecture : A Quantitative Approach -- Copyright -- Dedication -- Foreword -- Table of contents -- Preface -- Acknowledgments -- Chapter 1. Fundamentals of quantitative design and analysis -- Chapter 2. Memory hierarchy design -- Chapter 3. Instruction-level parallelism and its exploitation -- Chapter 4. Data-level parallelism in vector, SIMD, and GPU architectures -- Chapter 5. Thread-level parallelism -- Chapter 6. Warehouse-scale computers to exploit request-level and data-level parallelism -- Appendix A. Instruction set principles -- Appendix B. Review of memory hierarchy -- Appendix C. Pipelining : Basic and intermediate concepts -- Online Appendices -- Appendix D. Storage systems -- Appendix E. Embedded systems / by Thomas M. Conte -- Appendix F. Interconnection networks / revised by Timothy M. Pinkston and José Duato -- Appendix G. Vector processors in more depth / revised by Krste Asanovic -- Appendix H. Hardware and software for VLIW and EPIC -- Appendix I. Large-scale multiprocessors and scientific applications -- Appendix J. Computer arithmetic / by David Goldberg -- Appendix K. Survey of instruction set architectures -- Appendix L. Historical perspectives and references -- References -- Index. | |
| 520 | |a 'Computer Architecture: A Quantitative Approach', Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book became a part of Intel's 2012 recommended reading list for developers, and it covers the revolution of mobile computing. The text also highlights the two most important factors in architecture today : parallelism and memory hierarchy. The six chapters that this book is composed of follow a consistent framework : explanation of the ideas in each chapter ; a "crosscutting issues" section, which presents how the concepts covered in one chapter connect with those given in other chapters ; a "putting it all together" section that links these concepts by discussing how they are applied in real machine ; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects. The first chapter of the book includes formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability. Chapter 2 discusses memory hierarchy and includes discussions about virtual machines, SRAM and DRAM technologies, and new material on Flash memory. The third chapter covers the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, followed by an introduction to vector architectures in the fourth chapter. Chapters 5 and 6 describe multicore processors and warehouse-scale computers (WSCs), respectively. | ||
| 546 | |a English. | ||
| 588 | 0 | |a Print version record. | |
| 590 | |a Knovel |b ACADEMIC - Computer Hardware Engineering | ||
| 650 | 0 | |a Computer architecture. | |
| 650 | 6 | |a Ordinateurs |x Architecture. | |
| 650 | 7 | |a COMPUTERS |x Systems Architecture |x General. |2 bisacsh | |
| 650 | 7 | |a Computer architecture |2 fast | |
| 700 | 1 | |a Patterson, David A., |e author. | |
| 700 | 1 | |a Asanović, Krste, |e contributor. | |
| 776 | 0 | 8 | |i Print version: |a Hennessy, John L. |t Computer architecture. |b Fifth edition. |d Waltham, MA : Morgan Kaufmann, [2012] |z 9780123838728 |w (DLC) 2011038128 |w (OCoLC)755102367 |
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