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A designer's guide to asynchronous VLSI /
"Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cambridge ; New York :
Cambridge University Press,
2010.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Beerel, Peter A. | |
| 245 | 1 | 2 | |a A designer's guide to asynchronous VLSI / |c Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti. |
| 260 | |a Cambridge ; |a New York : |b Cambridge University Press, |c 2010. | ||
| 300 | |a 1 online resource (xii, 339 pages) : |b illustrations | ||
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| 520 | |a "Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications"--Provided by publisher. | ||
| 520 | |a "This book provides an introduction to this diverse area of VLSI from a designer's point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future"--Provided by publisher. | ||
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith. | |
| 588 | 0 | |a Print version record. | |
| 590 | |a Knovel |b ACADEMIC - Computer Hardware Engineering | ||
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Computer-aided design. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction. | |
| 650 | 0 | |a Asynchronous circuits. | |
| 650 | 6 | |a Circuits intégrés à très grande échelle |x Conception assistée par ordinateur. | |
| 650 | 6 | |a Circuits asynchrones. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 7 | |a Asynchronous circuits. |2 fast |0 (OCoLC)fst00819871 | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Computer-aided design. |2 fast |0 (OCoLC)fst00975604 | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design and construction. |2 fast |0 (OCoLC)fst00975610 | |
| 700 | 1 | |a Ozdag, Recep O. | |
| 700 | 1 | |a Ferretti, Marcos. | |
| 776 | 0 | 8 | |i Print version: |a Beerel, Peter A. |t Designer's guide to asynchronous VLSI. |d Cambridge ; New York : Cambridge University Press, 2010 |z 9780521872447 |w (DLC) 2009042290 |w (OCoLC)459209613 |
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