ASIC and FPGA verification : a guide to component modeling /

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Munden, Richard
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam ; Boston : Elsevier, ©2005.
Colección:Morgan Kaufmann series in systems on silicon.
Temas:
Application-specific integrated circuits.
Circuits intégrés à la demande.
Application specific integrated circuits.
Application-specific integrated circuits
Digitalelektronik
Field programmable gate array
Hierarchische Simulation
Integrierte Schaltung
Kundenspezifische Schaltung
Verifikation
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Cover
  • ABOUT THE AUTHOR
  • Table of Contents
  • PREFACE
  • Historical Background
  • Verilog, VHDL, and the Origin of VITAL
  • The VITAL Specification
  • The Free Model Foundry
  • Structure of the Book
  • Intended Audience
  • Resources for Help and Information
  • Acknowledgments
  • PART I INTRODUCTION
  • CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION
  • 1.1 Why Models Are Needed
  • 1.2 Definition of a Model
  • 1.3 Design Methods and Models
  • 1.4 How Models Fit in the FPGA/ASIC Design Flow
  • 1.5 Where to Get Models
  • 1.6 Summary
  • CHAPTER 2 TOUR OF A SIMPLE MODEL
  • 2.1 Formatting
  • 2.2 Standard Interfaces
  • 2.3 Model Delays
  • 2.4 VITAL Additions
  • 2.5 Interconnect Delays
  • 2.6 Finishing Touches
  • 2.7 Summary
  • PART II RESOURCES AND STANDARDS
  • CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS
  • 3.1 STD_LOGIC_1164
  • 3.2 VITAL_Timing
  • 3.3 VITAL_Primitives
  • 3.4 VITAL_Memory
  • 3.5 FMF Packages
  • 3.6 Summary
  • CHAPTER 4 AN INTRODUCTION TO SDF
  • 4.1 Overview of an SDF File
  • 4.2 SDF Capabilities
  • 4.3 Summary
  • CHAPTER 5 ANATOMY OF A VITAL MODEL
  • 5.1 Level 0 Guidelines
  • 5.2 Level 1 Guidelines
  • 5.3 Summary
  • CHAPTER 6 MODELING DELAYS
  • 6.1 Delay Types and Glitches
  • 6.2 Distributed Delays
  • 6.3 Pin-to-Pin Delays
  • 6.4 Path Delay Procedures
  • 6.5 Using VPDs
  • 6.6 Generates and VPDs
  • 6.7 Device Delays
  • 6.8 Backannotating Path Delays
  • 6.9 Interconnect Delays
  • 6.10 Summary
  • CHAPTER 7 VITAL TABLES
  • 7.1 Advantages of Truth and State Tables
  • 7.2 Truth Tables
  • 7.3 State Tables
  • 7.4 Reducing Pessimism
  • 7.5 Memory Tables
  • 7.6 Summary
  • CHAPTER 8 TIMING CONSTRAINTS
  • 8.1 The Purpose of Timing Constraint Checks
  • 8.2 Using Timing Constraint Checks in VITAL Models
  • 8.3 Violations
  • 8.4 Summary
  • PART III MODELING BASICS
  • CHAPTER 9 MODELING COMPONENTS WITH REGISTERS
  • 9.1 Anatomy of a Flip-Flop
  • 9.2 Anatomy of a Latch
  • 9.3 Summary
  • CHAPTER 10 CONDITIONAL DELAYS AND TIMING CONSTRAINTS
  • 10.1 Conditional Delays in VITAL
  • 10.2 Conditional Delays in SDF
  • 10.3 Conditional Delay Alternatives
  • 10.4 Mapping SDF to VITAL
  • 10.5 Conditional Timing Checks in VITAL
  • 10.6 Summary
  • CHAPTER 11 NEGATIVE TIMING CONSTRAINTS
  • 11.1 How Negative Constraints Work
  • 11.2 Modeling Negative Constraints
  • 11.3 How Simulators Handle Negative Constraints
  • 11.4 Ramifications
  • 11.5 Summary
  • CHAPTER 12 TIMING FILES AND BACKANNOTATION
  • 12.1 Anatomy of a Timing File
  • 12.2 Separate Timing Specifications
  • 12.3 Importing Timing Values
  • 12.4 Custom Timing Sections
  • 12.5 Generating Timing Files
  • 12.6 Generating SDF Files
  • 12.7 Backannotation and Hierarchy
  • 12.8 Summary
  • PART IV ADVANCED MODELING
  • CHAPTER 13 ADDING TIMING TO YOUR RTL CODE
  • 13.1 Using VITAL to Simulate Your RTL
  • 13.2 The Basic Wrap.

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