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ASIC and FPGA verification : a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Elsevier,
©2005.
|
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000 a 4500 | ||
|---|---|---|---|
| 001 | KNOVEL_ocn435501490 | ||
| 003 | OCoLC | ||
| 005 | 20231027140348.0 | ||
| 006 | m o d | ||
| 007 | cr unu|||||||| | ||
| 008 | 090901s2005 ne a o 001 0 eng d | ||
| 010 | |z 2004557557 | ||
| 040 | |a UMI |b eng |e pn |c UMI |d OCLCQ |d CEF |d OCLCQ |d MERUC |d EBLCP |d ZCU |d E7B |d OCLCQ |d IDEBK |d DEBSZ |d KNOVL |d OCLCQ |d OCLCO |d KNOVL |d OCLCF |d OCLCQ |d AU@ |d KNOVL |d YDXCP |d OCLCQ |d OCLCO |d OCLCQ |d STF |d OCLCQ |d WYU |d OCLCA |d VT2 |d OCLCO |d OCLCQ |d COA |d INARC |d OCLCO | ||
| 019 | |a 123125318 |a 441788642 |a 506874150 |a 647497820 |a 772055975 |a 856958911 |a 1044278167 |a 1056403007 |a 1060784893 |a 1065071979 |a 1074325829 |a 1100827025 |a 1235840014 |a 1240532007 |a 1340110786 | ||
| 020 | |a 9780125105811 | ||
| 020 | |a 0125105819 | ||
| 020 | |a 0080475922 |q (electronic bk.) | ||
| 020 | |a 9780080475929 |q (electronic bk.) | ||
| 020 | |a 1592782485 |q (electronic bk. ; |q Adobe Reader) | ||
| 020 | |a 9781592782482 |q (electronic bk. ; |q Adobe Reader) | ||
| 024 | 8 | |a (WaSeSS)ssj0000073697 | |
| 029 | 1 | |a AU@ |b 000050415366 | |
| 029 | 1 | |a AU@ |b 000051560603 | |
| 029 | 1 | |a AU@ |b 000051860203 | |
| 029 | 1 | |a AU@ |b 000060063770 | |
| 029 | 1 | |a DEBSZ |b 355395622 | |
| 029 | 1 | |a GBVCP |b 871532166 | |
| 029 | 1 | |a HEBIS |b 291468837 | |
| 029 | 1 | |a NZ1 |b 14231592 | |
| 035 | |a (OCoLC)435501490 |z (OCoLC)123125318 |z (OCoLC)441788642 |z (OCoLC)506874150 |z (OCoLC)647497820 |z (OCoLC)772055975 |z (OCoLC)856958911 |z (OCoLC)1044278167 |z (OCoLC)1056403007 |z (OCoLC)1060784893 |z (OCoLC)1065071979 |z (OCoLC)1074325829 |z (OCoLC)1100827025 |z (OCoLC)1235840014 |z (OCoLC)1240532007 |z (OCoLC)1340110786 | ||
| 037 | |a CL0500000047 |b Safari Books Online | ||
| 050 | 4 | |a TK7874.6 |b .M86 2005 | |
| 082 | 0 | 4 | |a 621.3815 |2 22 |
| 084 | |a 53.57 |2 bcl | ||
| 049 | |a UAMI | ||
| 100 | 1 | |a Munden, Richard. | |
| 245 | 1 | 0 | |a ASIC and FPGA verification : |b a guide to component modeling / |c Richard Munden. |
| 260 | |a Amsterdam ; |a Boston : |b Elsevier, |c ©2005. | ||
| 300 | |a 1 online resource (xx, 316 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 500 | |a Includes index. | ||
| 505 | 0 | |a Cover -- ABOUT THE AUTHOR -- Table of Contents -- PREFACE -- Historical Background -- Verilog, VHDL, and the Origin of VITAL -- The VITAL Specification -- The Free Model Foundry -- Structure of the Book -- Intended Audience -- Resources for Help and Information -- Acknowledgments -- PART I INTRODUCTION -- CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION -- 1.1 Why Models Are Needed -- 1.2 Definition of a Model -- 1.3 Design Methods and Models -- 1.4 How Models Fit in the FPGA/ASIC Design Flow -- 1.5 Where to Get Models -- 1.6 Summary -- CHAPTER 2 TOUR OF A SIMPLE MODEL -- 2.1 Formatting -- 2.2 Standard Interfaces -- 2.3 Model Delays -- 2.4 VITAL Additions -- 2.5 Interconnect Delays -- 2.6 Finishing Touches -- 2.7 Summary -- PART II RESOURCES AND STANDARDS -- CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS -- 3.1 STD_LOGIC_1164 -- 3.2 VITAL_Timing -- 3.3 VITAL_Primitives -- 3.4 VITAL_Memory -- 3.5 FMF Packages -- 3.6 Summary -- CHAPTER 4 AN INTRODUCTION TO SDF -- 4.1 Overview of an SDF File -- 4.2 SDF Capabilities -- 4.3 Summary -- CHAPTER 5 ANATOMY OF A VITAL MODEL -- 5.1 Level 0 Guidelines -- 5.2 Level 1 Guidelines -- 5.3 Summary -- CHAPTER 6 MODELING DELAYS -- 6.1 Delay Types and Glitches -- 6.2 Distributed Delays -- 6.3 Pin-to-Pin Delays -- 6.4 Path Delay Procedures -- 6.5 Using VPDs -- 6.6 Generates and VPDs -- 6.7 Device Delays -- 6.8 Backannotating Path Delays -- 6.9 Interconnect Delays -- 6.10 Summary -- CHAPTER 7 VITAL TABLES -- 7.1 Advantages of Truth and State Tables -- 7.2 Truth Tables -- 7.3 State Tables -- 7.4 Reducing Pessimism -- 7.5 Memory Tables -- 7.6 Summary -- CHAPTER 8 TIMING CONSTRAINTS -- 8.1 The Purpose of Timing Constraint Checks -- 8.2 Using Timing Constraint Checks in VITAL Models -- 8.3 Violations -- 8.4 Summary -- PART III MODELING BASICS -- CHAPTER 9 MODELING COMPONENTS WITH REGISTERS -- 9.1 Anatomy of a Flip-Flop -- 9.2 Anatomy of a Latch -- 9.3 Summary -- CHAPTER 10 CONDITIONAL DELAYS AND TIMING CONSTRAINTS -- 10.1 Conditional Delays in VITAL -- 10.2 Conditional Delays in SDF -- 10.3 Conditional Delay Alternatives -- 10.4 Mapping SDF to VITAL -- 10.5 Conditional Timing Checks in VITAL -- 10.6 Summary -- CHAPTER 11 NEGATIVE TIMING CONSTRAINTS -- 11.1 How Negative Constraints Work -- 11.2 Modeling Negative Constraints -- 11.3 How Simulators Handle Negative Constraints -- 11.4 Ramifications -- 11.5 Summary -- CHAPTER 12 TIMING FILES AND BACKANNOTATION -- 12.1 Anatomy of a Timing File -- 12.2 Separate Timing Specifications -- 12.3 Importing Timing Values -- 12.4 Custom Timing Sections -- 12.5 Generating Timing Files -- 12.6 Generating SDF Files -- 12.7 Backannotation and Hierarchy -- 12.8 Summary -- PART IV ADVANCED MODELING -- CHAPTER 13 ADDING TIMING TO YOUR RTL CODE -- 13.1 Using VITAL to Simulate Your RTL -- 13.2 The Basic Wrap. | |
| 588 | 0 | |a Print version record. | |
| 520 | |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification | ||
| 590 | |a Knovel |b ACADEMIC - Computer Hardware Engineering | ||
| 650 | 0 | |a Application-specific integrated circuits. | |
| 650 | 6 | |a Circuits intégrés à la demande. | |
| 650 | 7 | |a Application specific integrated circuits. |2 blmlsh | |
| 650 | 7 | |a Application-specific integrated circuits |2 fast | |
| 650 | 7 | |a Digitalelektronik |2 gnd | |
| 650 | 7 | |a Field programmable gate array |2 gnd | |
| 650 | 7 | |a Hierarchische Simulation |2 gnd | |
| 650 | 7 | |a Integrierte Schaltung |2 gnd | |
| 650 | 7 | |a Kundenspezifische Schaltung |2 gnd | |
| 650 | 7 | |a Verifikation |2 gnd | |
| 776 | 1 | |z 0080475922 |z 9780080475929 | |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://appknovel.uam.elogim.com/kn/resources/kpASICFPG4/toc |z Texto completo |
| 938 | |a ebrary |b EBRY |n ebr10128049 | ||
| 938 | |a ProQuest MyiLibrary Digital eBook Collection |b IDEB |n 100828 | ||
| 938 | |a YBP Library Services |b YANK |n 2352339 | ||
| 938 | |a YBP Library Services |b YANK |n 2586001 | ||
| 938 | |a Internet Archive |b INAR |n asicfpgaverifica0000mund | ||
| 994 | |a 92 |b IZTAP | ||