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Pipelined analog to digital converter and fault diagnosis /

Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, the...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Barua, Alok (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Bristol [England] (Temple Circus, Temple Way, Bristol BS1 6HG, UK) : IOP Publishing, [2020]
Colección:IOP ebooks. 2020 collection.
Temas:
Acceso en línea:Texto completo

MARC

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245 0 0 |a Pipelined analog to digital converter and fault diagnosis /  |c edited by Alok Barua. 
264 1 |a Bristol [England] (Temple Circus, Temple Way, Bristol BS1 6HG, UK) :  |b IOP Publishing,  |c [2020] 
300 |a 1 online resource (various pagings) :  |b illustrations (some color). 
336 |a text  |2 rdacontent 
337 |a electronic  |2 isbdmedia 
338 |a online resource  |2 rdacarrier 
490 1 |a IOP ebooks. [2020 collection] 
500 |a "Version: 20200301"--Title page verso. 
504 |a Includes bibliographical references. 
505 0 |a 1. A 1.8 V, 10 bit, 500 mega samples per second parallel pipelined analog-to-digital converter -- 1.1. Introduction -- 1.2. Pipelined analog-to-digital converter architecture -- 1.3. Operational transconductance amplifier (OTA) -- 1.4. Sample-and-hold amplifier -- 1.5. Multiplying digital-to-analog converter (MDAC) -- 1.6. Comparator -- 1.7. Conclusion  
505 8 |a 2. A. built-in self-test for a 1.8 V, 8 bit, 125 mega samples per second pipelined analog-to-digital converter -- 2.1. Organization of the chapter -- 2.2. Specifications of the pipelined ADC -- 2.3. Motivation and aims -- 2.4. Pipelined ADC architecture -- 2.5. A MATLAB model of the pipelined ADC -- 2.6. Results obtained in the Cadence environment -- 2.7. Built-in self-test (BIST) system -- 2.8. Simulation of the pipelined ADC -- 2.9. Future work  
505 8 |a 3. Design of an oscillation-based built-in self-test system for a 1.8 V, 8 bit, 125 mega samples per second pipelined analog-to-digital converter -- 3.1. Introduction -- 3.2. Oscillation-based BIST principles -- 3.3. Implementation of oscillation-based BIST -- 3.4. Introduction to ADC dynamic testing -- 3.5. Conclusion  
505 8 |a 4. An oscillation-based built-in self-test (BIST) system for dynamic performance parameter evaluation of an 8 bit, 100 MSPS pipelined ADC -- 4.1. Introduction -- 4.2. Oscillation-based BIST principles -- 4.3. Test stimulus generation -- 4.4. OTA-C filter -- 4.5. Dynamic parameter evaluation of a pipelined ADC -- 4.6. Fault analysis using the BIST system -- 4.7. Preparation of the layout and post-layout simulations -- 4.8. Conclusion  
505 8 |a 5. A reconfigurable built-in self-test architecture for a pipelined ADC -- 5.1. Introduction -- 5.2. The pipelined ADC -- 5.3. Oscillation-based built-in self-test system -- 5.4. Implementation of the ADC and OBIST -- 5.5. Conclusion. 
520 3 |a Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed. Chapter 1 discusses a 1.8V 10-bit 500 mega samples-per-second parallel pipelined ADC, describing the design of high speed, low power, low voltage ADC in CMOS technology. Chapter 2 introduces a BIST system where both the circuit and its diagnosis tool are implemented on the same chip. Chapter 3 examines the design of an oscillation-based BIST system for a 1.8V 8-bit 125-mega samples per second pipelined ADC. Chapter 4 focuses on the evaluation of dynamic parameters of a pipelined ADC with an oscillation-based BIST. Chapter 5 covers reconfigurable BIST architecture for pipelined ADCs. The book is an ideal reference for graduate students and researchers within electrical, electronics and computer engineering. 
521 |a Graduate students and researchers of electrical, electronics, computer engineering and their related branches of technology. 
530 |a Also available in print. 
538 |a Mode of access: World Wide Web. 
538 |a System requirements: Adobe Acrobat Reader, EPUB reader, or Kindle reader. 
545 |a Alok Barua is working as adjunct Professor in the Indian Institute of Technology (IIT), Jammu. With more than thirty three years of teaching experience at IIT, he has published multiple papers and books in his teaching and research areas--instrumentation, image processing, testing and fault diagnosis of analog and mixed signal circuit. He also holds a patent for the design of 'See Saw Bioreactor'. He has delivered invited lectures in many different universities in the USA, Europe, South East Asia, Far East and Mediterranean countries. 
588 0 |a Title from PDF title page (viewed on April 6, 2020). 
650 0 |a Analog-to-digital converters. 
650 0 |a Analog-to-digital converters  |x Testing. 
650 7 |a Circuits & components.  |2 bicssc 
650 7 |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI.  |2 bisacsh 
700 1 |a Barua, Alok,  |e editor. 
710 2 |a Institute of Physics (Great Britain),  |e publisher. 
776 0 8 |i Print version:  |z 9780750317306  |z 9780750317689 
830 0 |a IOP ebooks.  |p 2020 collection. 
856 4 0 |u https://iopscience.uam.elogim.com/book/978-0-7503-1732-0  |z Texto completo