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CMOS technology /
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York :
Nova Science Publishers, Inc.,
[2011]
|
| Colección: | Electrical engineering developments series.
|
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- CMOS TECHNOLOGY; CMOS TECHNOLOGY ; CONTENTS ; PREFACE ; PRINCIPLES, INTEGRATION AND CHALLENGES OF LITHOGRAPHY TECHNOLOGY FOR DEEP NANO-SCALE CMOS PATTERNING ; ABSTRACT ; 1. INTRODUCTION ; 2. EUV TOOL DEVELOPMENT: STATUS AND REQUIREMENTS ; 3. EUV LITHOGRAPHY CHALLENGES ; 3.1. EUV Source Power Requirement ; 3.2. EUV Mask Defect ; 3.3. EUV Mask Inspection ; 4. EUV SOURCE DEVELOPMENT ; 4.1. Gas Discharge Produced Plasma ; 4.2. Laser Produced Plasma ; 5. EUV RESIST DEVELOPMENT ; 6. EUV IMAGING WITH MULTILAYER MIRRORS ; 6.1. EUV Mirror Structure ; 6.2. Flare Impact on EUV Imaging.
- 7. EUV PHASE-SHIFTING MASKS 8. SUMMARY OF MASK BASED EUV LITHOGRAPHY ; 9. MASKLESS EUV LITHOGRAPHY ; 10. IMAGING THEORY OF PROJECTION LITHOGRAPHY ; 10.1. Basic Principles of Electromagnetic Field and Geometrical Optics ; 10.2. Light Propagation and Spatial Coherence ; 10.3. Spectral Analysis of Image Formation ; 10.4. Oblique Illumination and Partial Coherence ; 10.5. Resolution Enhancement Techniques ; 10.6. DUV Immersion Lithography ; 10.7. Vector Imaging Theory and Polarization ; 10.8. EUV Multilayer Reflective Optics ; 11. MULTIPLE PATTERNING TECHNOLOGIES ; 11.1. Double Patterning.
- 11.2. Self-aligned Triple and Quadruple Patterning SUMMARY ; REFERENCES ; VARIABILITY AND RELIABILITY IN ULTRA-SCALED MOS DEVICES: EVALUATION AT THE NANOSCALE AND IMPACT ON DEVICE AND CIRCUIT FUNCTIONALITY ; ABSTRACT ; INTRODUCTION ; NANOSCALE CHARACTERIZATION OF GATE OXIDE RELATED VARIABILITY ; Experimental Set-up and Sample Description ; Physical Characterization ; Electrical Characterization of the as-Grown High-K Stacks ; Charge Trapping after Electrical Stress ; TIME-DEPENDENT VARIABILITY OF DEVICES AND CIRCUITS ; Variability and Aging Experimental Characterization.
- SPICE Modelling of the Aging Mechanisms and Montecarlo Simulation of Device Variability SPICE Simulations: from Device Time-Dependent Variability to Circuit Reliability ; CONCLUSIONS ; ACKNOWLEDGMENTS ; REFERENCES ; LINEAR AND NON-LINEAR APPLICATIONS OF CMOS DVCC ; ABSTRACT ; I. INTRODUCTION ; II. SURVEY OF SOME EXISTING DVCC BASED CIRCUITS ; A. Amplifiers ; B. Integrators ; C. Filters with Bi-Linear Transfer Functions ; D. Biquadratic Filters ; E. Sinusoidal Oscillators and Function Generators ; III. PROPOSED CIRCUITS ; A. Linear Equation Solver ; B. Linear Programming Circuit.
- C. Quadratic Programming Circuit D. Implementation of Logic Gates Using DVCC ; IV. SIMULATION RESULTS ; CONCLUSION ; REFERENCES ; COMPACT MODELING OF MULTI-GATE MOSFET INCLUDING HOT-CARRIER EFFECTS ; 1. INTRODUCTION ; 2. DEFECTS IN CMOS-BASED DEVICES ; 2.1. Bulk Defects ; 2.1.1. Origin of the problem ; 2.1.2. Characterization methods ; 2.2. Hot Carrier ; 2.2.1. Origin of the problem ; 2.2.2. Device Parameters degradation ; 3. MODELING OF MULTI-GATE MOSFETS INCLUDING HOT-CARRIERS EFFECTS ; 3.1. Hot-Carriers Effects in Subthreshold Regime ; 3.1.1. Surface potential.