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Robust design of digital circuits on foil /
A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry.
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cambridge :
Cambridge University Press,
2016.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000Ia 4500 | ||
|---|---|---|---|
| 001 | EBSCO_ocn958454885 | ||
| 003 | OCoLC | ||
| 005 | 20231017213018.0 | ||
| 006 | m o d | ||
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| 008 | 160916s2016 enk ob 001 0 eng d | ||
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| 020 | |a 9781316657706 |q (electronic bk.) | ||
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| 020 | |z 9781316411483 | ||
| 020 | |z 1316411486 | ||
| 020 | |z 9781107127012 | ||
| 020 | |z 1107127017 | ||
| 035 | |a (OCoLC)958454885 |z (OCoLC)958357313 |z (OCoLC)958783459 |z (OCoLC)959273872 |z (OCoLC)959535177 |z (OCoLC)959950332 |z (OCoLC)960086995 |z (OCoLC)960087699 | ||
| 037 | |a 954941 |b MIL | ||
| 050 | 4 | |a TK7868.L6 |b M96 2016 | |
| 072 | 7 | |a TEC |x 009070 |2 bisacsh | |
| 082 | 0 | 4 | |a 621.39/5 |2 23 |
| 084 | |a TEC008010 |2 bisacsh | ||
| 049 | |a UAMI | ||
| 100 | 1 | |a Myny, Kris, |d 1980- |e author. | |
| 245 | 1 | 0 | |a Robust design of digital circuits on foil / |c Kris Myny, Jan Genoe, Wim Dehaene. |
| 260 | |a Cambridge : |b Cambridge University Press, |c 2016. | ||
| 300 | |a 1 online resource | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 588 | 0 | |a Online resource; title from PDF title page (EBSCO, viewed September 19, 2016). | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Cover; Half-title; Title page; Copyright information; Epigraph; Table of contents; Preface; List of abbreviations; 1 Thin-Film Transistor Technologies on the Move? From Backplane Driver to Ubiquitous Circuit Enabler?; 1.1 Backplanes for Active Matrix Displays; 1.1.1 Amorphous Silicon; 1.1.2 Low-Temperature Polycrystalline Silicon; 1.1.3 Organic Thin-Film Transistors; 1.1.4 Metal-Oxide Thin-Film Transistors; 1.1.5 Current TFT Technology Overview; 1.1.6 Options for Flexible Displays; 1.2 Large Area Sensors and Circuits (On Foil); 2 Organic and Metal-Oxide Thin-Film Transistors. | |
| 505 | 8 | |a 2.1 Device Configurations2.2 Operation Principle; 2.2.1 Operation Principle of a Single-Gate Transistor; 2.2.2 Technology Options for Multiple Threshold Voltages; 2.3 Typical Layout Rules in the Technologies Used in This Book; 2.4 Technologies Used in This Book; 2.4.1 Organic p-Type Technology of Polymer Vision; 2.4.2 Organic p-Type Dual-Gate Technology of Polymer Vision; 2.4.3 Pentacene (p-Type) Thin-Film Transistors on Al2O3 as Gate Dielectric; 2.4.4 a-IGZO (n-Type) Technology on Al2O3 as Gate Dielectric; 2.4.5 Hybrid Complementary Organic/Metal-Oxide Technology. | |
| 505 | 8 | |a 2.4.6 Hybrid Complementary Organic/Metal-Oxide Technology on PEN-Foil2.5 Trends in Circuit Integration; 2.5.1 Display Periphery; 2.5.2 Digital Logic; 2.5.3 Analog Circuits; 2.6 Summary; 3 Basic Gates; 3.1 Figures-of-Merit; 3.2 Logic Families; 3.3 Unipolar Logic; 3.3.1 Single VT, Depletion-Load, or Zero-VGS-Load Logic; 3.3.1.1 VTC of the Zero-VGS-Load Inverter; 3.3.1.2 Static Parameters of the Zero-VGS-Load Inverter; VM; Gain; 3.3.1.3 Dynamic Behavior of the Zero-VGS-Load Inverter; Study of the Zero-VGS-Load Capacitors; 3.3.2 Dual VT, Zero-VGS-Load Logic by Dual-Gate TFTs. | |
| 505 | 8 | |a 3.3.2.1 VTC of a Dual-VT Zero-VGS-Load Inverter3.3.2.2 Dual-Gate Zero-VGS-Load Inverter; 3.3.2.3 Optimized Dual-Gate Zero-VGS-Load Inverter; 3.3.3 Single VT, Enhancement-Load, or Diode-Load Logic; 3.3.3.1 VTC of the Diode-Load Inverter; 3.3.3.2 Static Behavior of the Diode-Load Inverter; VM; Gain; 3.3.3.3 Dynamic Behavior of the Diode-Load Inverter; Study of the Diode-Load Capacitances; 3.3.4 Dual VT, Diode-Load Logic in Dual-Gate Technologies; 3.4 Complementary Logic; 3.4.1 VTC of the Complementary Inverter; 3.4.2 Static Behavior of the Complementary Inverter; 3.4.2.1 VM; 3.4.2.2 Gain. | |
| 505 | 8 | |a 3.4.3 Dynamic Behavior of the Complementary Inverter3.4.3.1 Study of the Complementary Inverter Capacitances; 3.5 Conclusions; 3.6 Suggestions to Improve the Inverter Performance; 3.6.1 Level-Shifter; 3.6.2 Self-Aligned Technology; 4 Variability; 4.1 Classifications; 4.2 Sources of Process Variation; 4.2.1 Semiconductor; 4.2.1.1 Dielectric; 4.2.2 Contacts; 4.2.3 Foil; 4.3 Influence of Parameter Variation on the Yield of Logic Circuits; 4.4 How to Cope with WID and D2D Parameter Variations; 4.4.1 Designing with WID Variations; 4.4.2 Designing with D2D Variations -- Corner Analysis. | |
| 520 | |a A practical guide to the theory and applications of TFT technologies and circuit designs for those in academia and in industry. | ||
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 650 | 0 | |a Logic circuits. | |
| 650 | 0 | |a Flexible electronics |x Materials. | |
| 650 | 0 | |a Thin film transistors. | |
| 650 | 0 | |a Digital electronics. | |
| 650 | 0 | |a Metal foils. | |
| 650 | 6 | |a Circuits logiques. | |
| 650 | 6 | |a Électronique flexible |x Matériaux. | |
| 650 | 6 | |a Transistors à couches minces. | |
| 650 | 6 | |a Électronique numérique. | |
| 650 | 6 | |a Feuilles de métal. | |
| 650 | 7 | |a foil (metal by form) |2 aat | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Mechanical. |2 bisacsh | |
| 650 | 7 | |a Digital electronics |2 fast | |
| 650 | 7 | |a Logic circuits |2 fast | |
| 650 | 7 | |a Metal foils |2 fast | |
| 650 | 7 | |a Thin film transistors |2 fast | |
| 700 | 1 | |a Genoe, Jan, |d 1965- |e author. | |
| 700 | 1 | |a Dehaene, Wim, |e author. | |
| 776 | 0 | 8 | |i Print version: |a Myny, Kris, 1980- |t Robust design of digital circuits on foil. |d Cambridge : Cambridge University Press, 2016 |z 9781107127012 |z 1107127017 |w (DLC) 2015047185 |w (OCoLC)933713815 |
| 856 | 4 | 0 | |u https://ebsco.uam.elogim.com/login.aspx?direct=true&scope=site&db=nlebk&AN=1296547 |z Texto completo |
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