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Electronic System-Level HW

Modern electronic systems consist of a fairly heterogeneous set of components. Today, a single system can be constituted by a hardware platform, frequently composed of a mix of analog and digital components, and by several software application layers. The hardware can include several heterogeneous m...

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Detalles Bibliográficos
Clasificación:	Libro Electrónico
Autor principal:	Pomante, Luigi
Formato:	Electrónico eBook
Idioma:	Inglés
Publicado:	Aalborg : River Publishers, 2016.
Colección:	River Publishers series in circuits and systems.
Temas:	System design. Electronic systems. Conception de systèmes. Systèmes électroniques. SCIENCE / Energy TECHNOLOGY / Electricity Electronic books.
Acceso en línea:	Texto completo

Tabla de Contenidos:

Front Cover
Half Title Page
RIVER PUBLISHERS SERIES IN CIRCUITS AND SYSTEMS
Title Page
Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems
Copyright Page
Dedication
Contents
Preface
Acknowledgments
List of Figures
List of Tables
List of Abbreviations
Part 1
System-Level Co-Design of Heterogeneous
Chapter 1
Introduction
Chapter 2
Background
2.1 Heterogeneous Multi-Processor Embedded Systems
2.1.1 Existing Projects
2.1.2 Design Issues
2.2 Concurrent HW/SW Design
2.2.1 State-of-the-Art
2.3 Conclusion
Chapter 3
The Proposed Approach
3.1 The Reference Environment:TOSCA
3.1.1 The Specification Language
3.1.2 Intermediate Representations
3.1.3 The Target Architecture
3.1.4 Overview of the Design Flow
3.2 The Proposed Environment:TOHSCA
3.2.1 Target Architecture
3.3 Conclusion
Chapter 4
System-Level Co-Specification
4.1 System-Level Specification Languages
4.2 Reference Language
4.2.1 OCCAM
4.3 Internal Models
4.3.1 Statement-Level Internal Model
4.3.2 Procedure-Level Internal Model
4.4 Conclusion
Chapter 5
Metrics for Co-Analysis
5.1 Characterization
5.1.1 GPP Architectural Features
5.1.2 DSP Architectural Features
5.1.3 ASIC-like Devices Architectural Features
5.2 The Proposed Approach
5.2.1 Model and Methodology
5.2.2 The Tool
5.2.3 Validation
5.3 Conclusion
Chapter 6
System-Level Co-Estimations
6.1 Characterization
6.1.1 Performance Estimation
6.2 The Proposed Approach
6.2.1 Model and Methodology
6.2.2 Application of the model to OCCAM2
6.2.3 The Tool
6.2.4 Validation
6.3 Conclusion
Chaptere 7
System-Level Partitioning
7.1 Characterization
7.2 The Proposed Approach
7.2.1 Model and Methodology
7.2.2 The Tool.
7.2.3 Validation
7.3 Conclusion
Chapter 8
System-Level Co-Simulation
8.1 Characterization
8.2 The Proposed Approach
8.2.1 Model and Methodology
8.2.2 The Tool
8.2.3 Validation
8.3 Conclusion
Chapter 9
Case Studies
9.1 Case Study 1
9.1.1 Co-specification
9.1.2 Co-analysis
9.1.3 Co-estimation
9.1.4 Functional Co-simulation
9.1.5 Load Estimation
9.1.6 System Design Exploration
9.1.7 Toward the Low-level Co-design Flow
9.2 Case Study 2
9.2.1 Co-specification
9.2.2 Co-analysis
9.2.3 Co-estimation
9.2.4 Functional Co-simulation
9.2.5 Load Estimation
9.2.6 System Design Exploration
9.2.7 Toward a Low-level Co-design Flow
9.3 Conclusion
Conclusions (Part 1)
Part 2
January 2002-August 2014
Chapter 10
System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems
10.1 Introduction
10.2 Reference Co-Design Flow
10.3 Specification
10.4 Target HW Architecture
10.5 Design Space Exploration
10.5.1 First Phase
10.5.2 Second Phase
10.5.3 Illustrative Example
10.6 Conclusion
Chapter 11
SystemC-Based ESL Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems
11.1 Introduction
11.2 Reference ESL HW/SW Co-Design Flow
11.2.1 System Behavior Model
11.2.2 Technologies Library
11.2.3 Functional Simulation
11.2.4 Co-Analysis and Co-Estimation
11.2.5 Design Space Exploration
11.2.6 Algorithm-Level Flow
11.2.7 Reference Template HW Architecture
11.3 SystemC-Based ESL HW/SW Co-Design Environment
11.3.1 System Behavior Model
11.3.2 Functional Simulation
11.3.3 Co-Analysis and Co-Estimation
11.3.4 Design Space Exploration
11.4 SystemC-Based ESL Design Space Exploration
11.4.1 HW/SW Partitioning, Mapping, and Architecture Definition (1st Phase).
11.4.1.1 Inputs modeling
11.4.1.2 Technologies library modeling
11.4.1.3 PAM specification modeling
11.4.1.4 Optimization engine, individuals, and allocation modeling
11.4.2 Timing Co-Simulation
11.5 FIR-FIR-GCD Case Study
11.6 Conclusion
References
Index
About the Author
Back Cover.

Electronic System-Level HW

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