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Electronic System-Level HW
Modern electronic systems consist of a fairly heterogeneous set of components. Today, a single system can be constituted by a hardware platform, frequently composed of a mix of analog and digital components, and by several software application layers. The hardware can include several heterogeneous m...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Aalborg :
River Publishers,
2016.
|
| Colección: | River Publishers series in circuits and systems.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Pomante, Luigi. | |
| 245 | 1 | 0 | |a Electronic System-Level HW |c SW Co-Design of Heterogeneous Multi-Processor Embedded Systems. |
| 260 | |a Aalborg : |b River Publishers, |c 2016. | ||
| 300 | |a 1 online resource (272 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a River Publishers Series in Circuits and Systems | |
| 588 | 0 | |a Print version record. | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Front Cover -- Half Title Page -- RIVER PUBLISHERS SERIES IN CIRCUITS AND SYSTEMS -- Title Page -- Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems -- Copyright Page -- Dedication -- Contents -- Preface -- Acknowledgments -- List of Figures -- List of Tables -- List of Abbreviations -- Part 1 -- System-Level Co-Design of Heterogeneous -- Chapter 1 -- Introduction -- Chapter 2 -- Background -- 2.1 Heterogeneous Multi-Processor Embedded Systems -- 2.1.1 Existing Projects -- 2.1.2 Design Issues -- 2.2 Concurrent HW/SW Design -- 2.2.1 State-of-the-Art -- 2.3 Conclusion -- Chapter 3 -- The Proposed Approach -- 3.1 The Reference Environment:TOSCA -- 3.1.1 The Specification Language -- 3.1.2 Intermediate Representations -- 3.1.3 The Target Architecture -- 3.1.4 Overview of the Design Flow -- 3.2 The Proposed Environment:TOHSCA -- 3.2.1 Target Architecture -- 3.3 Conclusion -- Chapter 4 -- System-Level Co-Specification -- 4.1 System-Level Specification Languages -- 4.2 Reference Language -- 4.2.1 OCCAM -- 4.3 Internal Models -- 4.3.1 Statement-Level Internal Model -- 4.3.2 Procedure-Level Internal Model -- 4.4 Conclusion -- Chapter 5 -- Metrics for Co-Analysis -- 5.1 Characterization -- 5.1.1 GPP Architectural Features -- 5.1.2 DSP Architectural Features -- 5.1.3 ASIC-like Devices Architectural Features -- 5.2 The Proposed Approach -- 5.2.1 Model and Methodology -- 5.2.2 The Tool -- 5.2.3 Validation -- 5.3 Conclusion -- Chapter 6 -- System-Level Co-Estimations -- 6.1 Characterization -- 6.1.1 Performance Estimation -- 6.2 The Proposed Approach -- 6.2.1 Model and Methodology -- 6.2.2 Application of the model to OCCAM2 -- 6.2.3 The Tool -- 6.2.4 Validation -- 6.3 Conclusion -- Chaptere 7 -- System-Level Partitioning -- 7.1 Characterization -- 7.2 The Proposed Approach -- 7.2.1 Model and Methodology -- 7.2.2 The Tool. | |
| 505 | 8 | |a 7.2.3 Validation -- 7.3 Conclusion -- Chapter 8 -- System-Level Co-Simulation -- 8.1 Characterization -- 8.2 The Proposed Approach -- 8.2.1 Model and Methodology -- 8.2.2 The Tool -- 8.2.3 Validation -- 8.3 Conclusion -- Chapter 9 -- Case Studies -- 9.1 Case Study 1 -- 9.1.1 Co-specification -- 9.1.2 Co-analysis -- 9.1.3 Co-estimation -- 9.1.4 Functional Co-simulation -- 9.1.5 Load Estimation -- 9.1.6 System Design Exploration -- 9.1.7 Toward the Low-level Co-design Flow -- 9.2 Case Study 2 -- 9.2.1 Co-specification -- 9.2.2 Co-analysis -- 9.2.3 Co-estimation -- 9.2.4 Functional Co-simulation -- 9.2.5 Load Estimation -- 9.2.6 System Design Exploration -- 9.2.7 Toward a Low-level Co-design Flow -- 9.3 Conclusion -- Conclusions (Part 1) -- Part 2 -- January 2002-August 2014 -- Chapter 10 -- System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems -- 10.1 Introduction -- 10.2 Reference Co-Design Flow -- 10.3 Specification -- 10.4 Target HW Architecture -- 10.5 Design Space Exploration -- 10.5.1 First Phase -- 10.5.2 Second Phase -- 10.5.3 Illustrative Example -- 10.6 Conclusion -- Chapter 11 -- SystemC-Based ESL Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems -- 11.1 Introduction -- 11.2 Reference ESL HW/SW Co-Design Flow -- 11.2.1 System Behavior Model -- 11.2.2 Technologies Library -- 11.2.3 Functional Simulation -- 11.2.4 Co-Analysis and Co-Estimation -- 11.2.5 Design Space Exploration -- 11.2.6 Algorithm-Level Flow -- 11.2.7 Reference Template HW Architecture -- 11.3 SystemC-Based ESL HW/SW Co-Design Environment -- 11.3.1 System Behavior Model -- 11.3.2 Functional Simulation -- 11.3.3 Co-Analysis and Co-Estimation -- 11.3.4 Design Space Exploration -- 11.4 SystemC-Based ESL Design Space Exploration -- 11.4.1 HW/SW Partitioning, Mapping, and Architecture Definition (1st Phase). | |
| 505 | 8 | |a 11.4.1.1 Inputs modeling -- 11.4.1.2 Technologies library modeling -- 11.4.1.3 PAM specification modeling -- 11.4.1.4 Optimization engine, individuals, and allocation modeling -- 11.4.2 Timing Co-Simulation -- 11.5 FIR-FIR-GCD Case Study -- 11.6 Conclusion -- References -- Index -- About the Author -- Back Cover. | |
| 520 | |a Modern electronic systems consist of a fairly heterogeneous set of components. Today, a single system can be constituted by a hardware platform, frequently composed of a mix of analog and digital components, and by several software application layers. The hardware can include several heterogeneous microprocessors (e.g. GPP, DSP, GPU, etc.), dedicated ICs (ASICs and/or FPGAs), memories, a set of local connections between the system components, and some interfaces between the system and the environment (sensors, actuators, etc.). Therefore, on the one hand, multi-processor embedded systems are capable of meeting the demand of processing power and flexibility of complex applications. On the other hand, such systems are very complex to design and optimize, so that the design methodology plays a major role in determining the success of the products. For these reasons, to cope with the increasing system complexity, the approaches typically used today are oriented towards co-design methodologies working at the higher levels of abstraction. Unfortunately, such methodologies are typically customized for the specific application, suffer of a lack of generality and still need a considerable effort when real-size project are envisioned. Therefore, there is still the need for a general methodology able to support the designer during the high-level steps of a co-design flow, enabling an effective design space exploration before tackling the low-level steps and thus committing to the final technology. This should prevent costly redesign loops.In such a context, the work described in this book, composed of two parts, aims at providing models, methodologies and tools to support each step of the co-design flow of embedded systems implemented by exploiting heterogeneous multi-processor architectures mapped on distributed systems, as well as fully integrated onto a single chip. | ||
| 545 | 0 | |a Luigi Pomante | |
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 650 | 0 | |a System design. | |
| 650 | 0 | |a Electronic systems. | |
| 650 | 6 | |a Conception de systèmes. | |
| 650 | 6 | |a Systèmes électroniques. | |
| 650 | 7 | |a SCIENCE / Energy |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY / Electricity |2 bisacsh | |
| 650 | 7 | |a Electronic systems. |2 fast |0 (OCoLC)fst00907484 | |
| 650 | 7 | |a System design. |2 fast |0 (OCoLC)fst01141401 | |
| 655 | 0 | |a Electronic books. | |
| 776 | 0 | 8 | |i Print version: |a Pomante, Luigi. |t Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems. |d Aalborg : River Publishers, ©2016 |z 9788793379381 |
| 830 | 0 | |a River Publishers series in circuits and systems. | |
| 856 | 4 | 0 | |u https://ebsco.uam.elogim.com/login.aspx?direct=true&scope=site&db=nlebk&AN=1800530 |z Texto completo |
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