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The logic of digital circuits /

Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Glebov, Alexei L. (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York : nova science publishers, [2016]
Colección:Electronics and telecommunications research
Temas:
Acceso en línea:Texto completo

MARC

LEADER 00000cam a2200000 i 4500
001 EBSCO_ocn949850957
003 OCoLC
005 20231017213018.0
006 m o d
007 cr |||||||||||
008 160513s2016 nyu ob 001 0 eng
010 |a  2016022546 
040 |a DLC  |b eng  |e rda  |c DLC  |d OCLCF  |d N$T  |d YDX  |d EBLCP  |d IDB  |d SNK  |d DKU  |d IGB  |d D6H  |d VTS  |d RRP  |d AGLDB  |d G3B  |d S8J  |d S9I  |d STF  |d DLC  |d OCLCO  |d OCLCQ  |d OCLCO 
019 |a 960447489  |a 961006085  |a 961937706  |a 967763658 
020 |a 9781634852395  |q (eBook) 
020 |a 1634852397 
020 |z 9781634842488  |q (softcover) 
020 |z 1634842480  |q (hardcover) 
029 1 |a AU@  |b 000057428982 
035 |a (OCoLC)949850957  |z (OCoLC)960447489  |z (OCoLC)961006085  |z (OCoLC)961937706  |z (OCoLC)967763658 
042 |a pcc 
050 1 0 |a TK7868.D5 
072 7 |a TEC  |x 009070  |2 bisacsh 
082 0 0 |a 621.39/5  |2 23 
049 |a UAMI 
245 0 4 |a The logic of digital circuits /  |c Alexey Glebov. 
263 |a 1606 
264 1 |a New York :  |b nova science publishers,  |c [2016] 
300 |a 1 online resource. 
336 |a text  |2 rdacontent 
337 |a computer  |2 rdamedia 
338 |a online resource  |2 rdacarrier 
347 |a data file  |2 rda 
490 0 |a Electronics and telecommunications research 
504 |a Includes bibliographical references and index. 
588 |a Description based on print version record and CIP data provided by publisher; resource not viewed. 
505 0 |a Preface; Chapter 1; Introduction to Binary Decision Diagrams; 1.1. Boolean Functions; 1.2. Boolean Circuits; 1.3. Boolean Formulae; 1.4. Shannon Trees; 1.5. Definition of BDD; 1.6. Operations on BDD; 1.7. Variable Ordering; 1.8. Applications; 1.9. Results of Numerical Experiments; References; Chapter 2; Boolean Algebras and Boolean Functions; 2.1. Sets; 2.1.1. Methods for Describing Sets; 2.1.2. Sets and Sequences; 2.1.3. Inclusion, Equality, Power, Empty Set; 2.1.4. Operation with Sets; 2.1.5. Partitions, Relations and Functions; 2.2. Definition of Boolean Algebra. 
505 8 |a 2.3. Examples of Boolean Algebras2.3.1. Algebra of Subsets of a Given Set; 2.3.2. Arithmetic Boolean Algebra; 2.3.3. Two-Element Boolean Algebra; 2.3.4. Stone's Theorem; 2.4. Inclusion Relation; 2.4.1. Intervals; 2.5. Some Useful Properties; 2.6. Formulae and Functions; 2.6.1. Boolean Formulae; 2.6.2. Boolean Functions; 2.7. Shannon's Expansion; 2.8. Canonical Forms; 2.9. Incompletely Specified Boolean Functions; 2.10. Boolean Algebras of Boolean Functions; References; Chapter 3; BDD: Data Structure and Algorithms for Operation with Boolean Functions; 3.1. Introduction; 3.1.1. Designations. 
505 8 |a 3.2. Representation3.3. Properties; 3.3.1. Examples of Functions; 3.3.3. Significantly Complex Functions; 3.4. Operations; 3.4.1. Data Structures; 3.4.2. Reduction; 3.4.3. Execution of Binary Operation (Apply); 3.4.4. Restriction; 3.4.5. Composition; 3.4.6. Satisfy Procedure; References; Chapter 4; BDD Efficient Implementation; 4.1. The Main Ideas; 4.1.1. Shared BDD; 4.1.2. Unique Table and Strong Canonical Form; 4.1.3. ITE Algorithm and Calculated Table; 4.1.4. Complemented Edges; References; Chapter 5; Series-Parallel BDD: Theory and Applications; 5.1. Introduction. 
505 8 |a 5.2. Definitions and Basic Properties5.3. Basic Operations; 5.3.1. Reordering; 5.3.2. Merging; 5.3.3. Decomposition; 5.3.4. Extraction; 5.4. SP-BDD and CMOS Circuits; 5.4.1. SP-Restriction; 5.4.2. Minimization of Enclosed SP-BDD; 5.5. SP-BDD Applications; 5.5.1. CMOS Circuit Resynthesis; 5.5.2. Worst-Case Elmore Delay for Transistor SP-Network; Conclusion; References; Chapter 6; Simple Logic Implications (SLI) and False-Noise Analysis; 6.1. Introduction; 6.2. Computing Logic Implications; 6.2.1. Generation of SLIs for Simple Gates; 6.2.2. Generating SLIs for Complex Gates. 
505 8 |a 6.2.3. Propagation of SLIs6.2.4. Generation of SLIs with Tristate Gates; 6.3. False Noise Analysis Using SLIs; 6.3.1. Forming the Constraint Graph; 6.3.2. Solving MWIS Problem; 6.4. Extension to Timed SLIs; 6.4.1. Basic Definitions; 6.4.2. Propagation of Timed SLIs; 6.4.3. Using Timed SLIs for False Noise Analysis; 6.5. Implementation and Experimental Results; Conclusion; References; Chapter 7; Detecting False Paths in Static Timing Analysis Based on Logic Implications; 7.1. Introduction; 7.2. Static Timing Analysis; 7.3. Forming Logic Constraints. 
590 |a eBooks on EBSCOhost  |b EBSCO eBook Subscription Academic Collection - Worldwide 
650 0 |a Digital electronics. 
650 0 |a Binary system (Mathematics) 
650 0 |a Algebra, Boolean. 
650 6 |a Électronique numérique. 
650 6 |a Système binaire (Mathématiques) 
650 6 |a Algèbre de Boole. 
650 7 |a TECHNOLOGY & ENGINEERING  |x Mechanical.  |2 bisacsh 
650 7 |a Algebra, Boolean  |2 fast 
650 7 |a Binary system (Mathematics)  |2 fast 
650 7 |a Digital electronics  |2 fast 
700 1 |a Glebov, Alexei L.,  |e editor. 
776 0 8 |i Print version:  |t Logic of digital circuits  |d New York : nova science publishers, [2016]  |z 9781634842488  |w (DLC) 2016017074 
856 4 0 |u https://ebsco.uam.elogim.com/login.aspx?direct=true&scope=site&db=nlebk&AN=1367367  |z Texto completo 
938 |a YBP Library Services  |b YANK  |n 12933126 
938 |a EBSCOhost  |b EBSC  |n 1367367 
938 |a EBL - Ebook Library  |b EBLB  |n EBL4728113 
994 |a 92  |b IZTAP