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20231017213018.0 |
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151005s2015 nju ob 001 0 eng d |
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|a 941700320
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|a 9789814699020
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|a 9814699020
|q (electronic bk.)
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|z 9789814699006
|q (hardback ;
|q alk. paper)
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|z 9814699004
|q (hardback ;
|q alk. paper)
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|z 9789814699013
|q (pbk. ;
|q alk. paper)
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|q (pbk. ;
|q alk. paper)
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|b BV043784895
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|b 47287070X
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|a (OCoLC)922922497
|z (OCoLC)941700320
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|a TK7874.893
|b .Y83 2015
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|a TEC
|x 009070
|2 bisacsh
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|a 621.3815
|2 23
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| 049 |
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|a UAMI
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| 100 |
1 |
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|a Yu, Hao
|c (Electrical engineer),
|e author.
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| 245 |
1 |
0 |
|a Advances in 3D integrated circuits and systems /
|c by Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore).
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| 264 |
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1 |
|a New Jersey :
|b World Scientific,
|c 2015.
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|c ©2016
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|a 1 online resource
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 490 |
1 |
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|a Series on emerging technologies in circuits and systems
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| 504 |
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|a Includes bibliographical references and index.
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| 588 |
0 |
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|a Print version record.
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| 505 |
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|a Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design.
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|a 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner.
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|a 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model.
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| 505 |
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|a 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression.
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| 505 |
8 |
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|a 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation.
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| 590 |
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|a eBooks on EBSCOhost
|b EBSCO eBook Subscription Academic Collection - Worldwide
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| 650 |
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|a Three-dimensional integrated circuits.
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| 650 |
|
6 |
|a Circuits intégrés tridimensionnels.
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| 650 |
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7 |
|a TECHNOLOGY & ENGINEERING
|x Mechanical.
|2 bisacsh
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| 650 |
|
7 |
|a Three-dimensional integrated circuits.
|2 fast
|0 (OCoLC)fst01765149
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| 700 |
1 |
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|a Tan, Chuan Seng.
|
| 776 |
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|i Print version:
|z 9789814699006
|z 9814699004
|w (DLC) 2015020144
|w (OCoLC)910475568
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| 830 |
|
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|a Series on emerging technologies in circuits and systems ;
|v vol. 1.
|
| 856 |
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