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Network processor design : issues and practices. Volume 1 /
As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from ta...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Burlington :
Elsevier,
2002.
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| Colección: | Morgan Kaufmann Series in Computer Architecture and Design.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 245 | 0 | 0 | |a Network processor design : |b issues and practices. |n Volume 1 / |c edited by Patrick Crowley [and others]. |
| 260 | |a Burlington : |b Elsevier, |c 2002. | ||
| 300 | |a 1 online resource (353 pages) | ||
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| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann Series in Computer Architecture and Design ; |v v. 1 | |
| 505 | 0 | |a Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors. | |
| 505 | 8 | |a Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing. | |
| 505 | 8 | |a Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors. | |
| 505 | 8 | |a Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU. | |
| 505 | 8 | |a Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors. | |
| 520 | |a As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and dat. | ||
| 588 | 0 | |a Print version record. | |
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| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
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| 700 | 1 | |a Crowley, Patrick, |d 1974- | |
| 700 | 1 | |a Hadimioglu, Haldun. | |
| 700 | 1 | |a Onufryk, Peter Z. | |
| 776 | 0 | 8 | |i Print version: |a Franklin, Mark A. |t Network Processor Design : Issues and Practices, Volume 1. |d Burlington : Elsevier, ©2002 |z 9781558608757 |
| 830 | 0 | |a Morgan Kaufmann Series in Computer Architecture and Design. | |
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