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Skew-tolerant circuit design /
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers,
©2001.
|
| Colección: | Morgan Kaufmann series in computer architecture and design.
|
| Temas: | |
| Acceso en línea: | Texto completo Texto completo |
MARC
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| 037 | |a 97012:97012 |b Elsevier Science & Technology |n http://www.sciencedirect.com | ||
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| 100 | 1 | |a Harris, David |q (David Lewis) | |
| 245 | 1 | 0 | |a Skew-tolerant circuit design / |c David Harris. |
| 260 | |a San Francisco : |b Morgan Kaufmann Publishers, |c ©2001. | ||
| 300 | |a 1 online resource (xiv, 223 pages) : |b illustrations. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
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| 490 | 1 | |a Morgan Kaufmann series in computer architecture and design | |
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Chapter 1 -- Introduction -- Chapter 2 -- Fundamental Concepts -- Chapter 3 -- IP Switching -- Chapter 4 -- Tag Switching -- Chapter 5 -- MPLS Core Protocols -- Chapter 6 -- Quality of Service -- Chapter 7 -- ConstraintƯbased routing -- Chapter 8 -- Virtual Private Networks. | |
| 520 | |a As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises. | ||
| 546 | |a English. | ||
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Timing circuits |x Design and construction. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction. | |
| 650 | 0 | |a Synchronization. | |
| 650 | 6 | |a Synchronisation. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Integrated. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x General. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design and construction |2 fast | |
| 650 | 7 | |a Synchronization |2 fast | |
| 650 | 7 | |a Timing circuits |x Design and construction |2 fast | |
| 776 | 0 | 8 | |i Print version: |a Harris, David (David Lewis). |t Skew-tolerant circuit design. |d San Francisco : Morgan Kaufmann Publishers, ©2001 |w (DLC) 00036538 |
| 830 | 0 | |a Morgan Kaufmann series in computer architecture and design. | |
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