System-on-chip test architectures : nanometer design for testability /

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Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semic...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Wang, Laung-Terng, Stroud, Charles E., Touba, Nur A.
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008.
Colección:Morgan Kaufmann series in systems on silicon.
Temas:
Systems on a chip > Testing.
Integrated circuits > Very large scale integration > Testing.
Integrated circuits > Very large scale integration > Design.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic.
COMPUTERS > Logic Design.
Integrated circuits > Very large scale integration > Design
Integrated circuits > Very large scale integration > Testing
VLSI
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

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