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Logic-timing simulation and the degradation delay model /
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London :
Imperial College Press,
©2006.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Bellido, Manuel J., |d 1964- | |
| 245 | 1 | 0 | |a Logic-timing simulation and the degradation delay model / |c Manuel J. Bellido, Jorge Juan, Manuel Valencia. |
| 260 | |a London : |b Imperial College Press, |c ©2006. | ||
| 300 | |a 1 online resource (xvii, 267 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a data file | ||
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | 0 | |g Machine generated contents note: |g 1. |t Fundamentals of timing simulation -- |g 2. |t Delay models : evolution and trends -- |g 3. |t Degradation and inertial effects -- |g 4. |t CMOS inverter degradation delay model -- |g 5. |t Gate-level DDM -- |g 6. |t Logic level simulator design and implementation -- |g 7. |t DDM simulation results. |
| 520 | |a This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl | ||
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| 650 | 0 | |a Computer simulation. | |
| 650 | 0 | |a Mathematical models. | |
| 650 | 2 | |a Computer Simulation | |
| 650 | 2 | |a Models, Theoretical | |
| 650 | 6 | |a Simulation par ordinateur. | |
| 650 | 6 | |a Modèles mathématiques. | |
| 650 | 7 | |a simulation. |2 aat | |
| 650 | 7 | |a mathematical models. |2 aat | |
| 650 | 7 | |a COMPUTERS |x Computer Simulation. |2 bisacsh | |
| 650 | 7 | |a Computer simulation |2 fast | |
| 650 | 7 | |a Mathematical models |2 fast | |
| 700 | 1 | |a Juan Chico, Jorge. | |
| 700 | 1 | |a Valencia, Manuel. | |
| 776 | 0 | 8 | |i Print version: |a Bellido, Manuel J., 1964- |t Logic-timing simulation and the degradation delay model. |d London : Imperial College Press, ©2006 |z 1860945899 |w (OCoLC)64790367 |
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