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Verification techniques for system-level design /
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
©2008.
|
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Temas: | |
| Acceso en línea: | Texto completo Texto completo |
MARC
| LEADER | 00000cam a2200000 a 4500 | ||
|---|---|---|---|
| 001 | EBSCO_ocn182548558 | ||
| 003 | OCoLC | ||
| 005 | 20231017213018.0 | ||
| 006 | m o d | ||
| 007 | cr cnu---unuuu | ||
| 008 | 071127s2008 ne a ob 001 0 eng d | ||
| 040 | |a N$T |b eng |e pn |c N$T |d YDXCP |d OCLCQ |d E7B |d OCLCQ |d UMI |d CEF |d DKDLA |d NHM |d OCLCQ |d DEBSZ |d OCLCO |d OCLCQ |d VLB |d OCLCQ |d COO |d OCLCQ |d AZK |d COCUF |d AGLDB |d STF |d MOR |d PIFAG |d OCLCQ |d JBG |d U3W |d OCLCF |d WRM |d D6H |d OCLCQ |d VTS |d NRAMU |d INT |d VT2 |d OCLCQ |d REC |d LEAUB |d M8D |d OCLCQ |d K6U |d VLY |d OCLCO |d OCLCQ |d KSU |d OCLCQ |d OCLCO | ||
| 015 | |a GBA774751 |2 bnb | ||
| 016 | 7 | |z 013950010 |2 Uk | |
| 019 | |a 228148347 |a 435501525 |a 473204584 |a 647688877 |a 961678069 |a 962622419 |a 984796307 |a 988441714 |a 992073312 |a 1017997135 |a 1037704642 |a 1038696785 |a 1044303025 |a 1045448871 |a 1055383446 |a 1162261673 | ||
| 020 | |a 9780080553139 |q (electronic bk.) | ||
| 020 | |a 0080553133 |q (electronic bk.) | ||
| 020 | |a 1281049646 | ||
| 020 | |a 9781281049643 | ||
| 020 | |a 9786611049645 | ||
| 020 | |a 6611049649 | ||
| 020 | |z 9780123706164 |q (pbk.) | ||
| 020 | |z 0123706165 |q (pbk.) | ||
| 029 | 1 | |a AU@ |b 000043178405 | |
| 029 | 1 | |a AU@ |b 000051555307 | |
| 029 | 1 | |a CHNEW |b 001007339 | |
| 029 | 1 | |a DEBBG |b BV042305711 | |
| 029 | 1 | |a DEBBG |b BV043091834 | |
| 029 | 1 | |a DEBSZ |b 355395096 | |
| 029 | 1 | |a DEBSZ |b 367750201 | |
| 029 | 1 | |a DEBSZ |b 422169196 | |
| 029 | 1 | |a GBVCP |b 802390501 | |
| 029 | 1 | |a HEBIS |b 291468330 | |
| 029 | 1 | |a NZ1 |b 12541542 | |
| 029 | 1 | |a NZ1 |b 14540481 | |
| 029 | 1 | |a NZ1 |b 15189655 | |
| 035 | |a (OCoLC)182548558 |z (OCoLC)228148347 |z (OCoLC)435501525 |z (OCoLC)473204584 |z (OCoLC)647688877 |z (OCoLC)961678069 |z (OCoLC)962622419 |z (OCoLC)984796307 |z (OCoLC)988441714 |z (OCoLC)992073312 |z (OCoLC)1017997135 |z (OCoLC)1037704642 |z (OCoLC)1038696785 |z (OCoLC)1044303025 |z (OCoLC)1045448871 |z (OCoLC)1055383446 |z (OCoLC)1162261673 | ||
| 037 | |a CL0500000047 |b Safari Books Online | ||
| 050 | 4 | |a TK7895.E42 |b F95 2008eb | |
| 072 | 7 | |a TEC |x 008020 |2 bisacsh | |
| 072 | 7 | |a TEC |x 008010 |2 bisacsh | |
| 082 | 0 | 4 | |a 621.3815 |2 22 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Fujita, Masahiro, |d 1956- | |
| 245 | 1 | 0 | |a Verification techniques for system-level design / |c Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad. |
| 260 | |a Amsterdam ; |a Boston : |b Morgan Kaufmann Publishers, |c ©2008. | ||
| 300 | |a 1 online resource (viii, 240 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 504 | |a Includes bibliographical references and index. | ||
| 520 | 8 | |a This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology. | |
| 520 | 8 | |a Printbegrænsninger: Der kan printes kapitelvis. | |
| 505 | 0 | |a 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion. | |
| 588 | 0 | |a Print version record. | |
| 546 | |a English. | ||
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Systems on a chip |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Verification. | |
| 650 | 0 | |a Formal methods (Computer science) | |
| 650 | 6 | |a Circuits intégrés |x Vérification. | |
| 650 | 6 | |a Méthodes formelles (Informatique) | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Integrated. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x General. |2 bisacsh | |
| 650 | 7 | |a Systems on a chip |x Testing. |2 blmlsh | |
| 650 | 7 | |a Integrated circuits |x Verification. |2 blmlsh | |
| 650 | 7 | |a Formal methods (Computer science) |2 blmlsh | |
| 650 | 7 | |a Formal methods (Computer science) |2 fast | |
| 650 | 7 | |a Integrated circuits |x Verification |2 fast | |
| 700 | 1 | |a Ghosh, Indradeep, |d 1970- | |
| 700 | 1 | |a Prasad, Mukul. | |
| 776 | 0 | 8 | |i Print version: |a Fujita, Masahiro, 1956- |t Verification techniques for system-level design. |d Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008 |z 9780123706164 |z 0123706165 |w (DLC) 2007028038 |w (OCoLC)155126176 |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://ebsco.uam.elogim.com/login.aspx?direct=true&scope=site&db=nlebk&AN=210385 |z Texto completo |
| 856 | 4 | 0 | |u https://learning.oreilly.com/library/view/~/9780123706164/?ar |z Texto completo |
| 938 | |a ebrary |b EBRY |n ebr10203637 | ||
| 938 | |a EBSCOhost |b EBSC |n 210385 | ||
| 938 | |a YBP Library Services |b YANK |n 2737738 | ||
| 994 | |a 92 |b IZTAP | ||