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VHDL : coding and logic synthesis with Synopsys /

This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas. Synopsys is the dominant...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Lee, Weng Fook
Formato: Electrónico eBook
Idioma:Inglés
Publicado: San Diego : Academic Press, ©2000.
Temas:
Acceso en línea:Texto completo
Tabla de Contenidos:
  • List of Figures.
  • List of Tables.
  • List of Examples.
  • Preface.
  • Acknowledgement.
  • Trademarks.
  • I. VHDL CODING
  • 1. Introduction.
  • 2. VHDL Simulation and Synthesis Flow.
  • 3. Synthesizable Code for Basic Logic Components.
  • 4. Signal Versus Variable.
  • 5. Examples of Complex Synthesizable Code.
  • 6. Pipeline Microcontroller Synthesizable Design.
  • II. LOGIC SYNTHESIS WITH SYNOPSYS.
  • 7. Timing Considerations in Design.
  • 8. VHDL Synthesis with Timing Constraints.
  • 9. GTECH Instantiation.
  • 10. DesignWare Library.
  • 11. Testability Issues in Synthesis.
  • 12. FPGA Synthesis.
  • 13. Synthesis Links to Layout.
  • 14. Design Guideline to Follow for Efficient Synthesis.
  • 15. Appendix A (STD_LOGIC_1164 Library).
  • 16. Appendix B (Shifter Synthesis Results).
  • 17. Appendix C (Counter Synthesis Results).
  • 18. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation).
  • 19. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6).
  • 20. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6).
  • Glossary.
  • Bibliography.
  • Index.