Cargando…
Demystifying chipmaking /
This book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the engineers who solved so...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Oxford :
Elsevier/Newnes,
©2005.
|
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- CH 1: IC Fabrication Overview / CH 2: Support Technologies / CH 3: Forming Wells / CH 4: Isolate Active Areas (Shallow Trench Isolation) / CH 5: Building the Transistors / CH 6: First Level Metallization / CH 7: Multilevel Metal Interconnects and Dual Damascene / CH 8: Test and Assembly / APPENDIX A: Science Overview / APPENDIX B: Plasma Etch Supplement to Chapter 4.
- IC fabrication overview
- Introduction
- Support technologies
- Integrated circuit fabrication
- Test and assembly
- Summary
- Support technologies
- Introduction
- Contamination control
- Crystal growth and wafer preparation
- Circuit design
- Photomask and reticle preparation
- Forming wells
- Introduction
- Initial oxidation
- Photolithography
- Ion implantation
- Isolate active areas (shallow trench isolation)
- Introduction to shallow trench isolation
- Pad oxide growth
- Silicon Nitride deposition
- Photolithography for photo/etch
- From trenches in silicon dioxide
- Chemical mechanical polishing (CMP) to remove excess dioxide
- Wet etch removal of Silicon Nitride and pad oxide
- Building the transistors
- Introduction
- Thin film formation
- Poly gate formation
- Source/drain formation
- Salicide formation
- First level metallization
- Introduction
- Nitride and oxide depositions
- CMP planarization
- Photo/etch for contact holes
- Tungsten plug process
- Low-k dielectric process
- Copper first level interconnection process
- Multilevel metal interconnects and dual damascene
- Introduction
- Deposit barrier layer and intermetal dielectric
- Dual damascene process
- Form bonding pads
- Final passivation process
- Test and assembly
- Introduction
- Wafer and chip testing
- Assembly and packaging.