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ASIC and FPGA verification : a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco, Calif. :
Morgan Kaufmann,
©2005.
|
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Temas: | |
| Acceso en línea: | Texto completo Texto completo |
MARC
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| 100 | 1 | |a Munden, Richard. | |
| 245 | 1 | 0 | |a ASIC and FPGA verification : |b a guide to component modeling / |c Richard Munden. |
| 260 | |a San Francisco, Calif. : |b Morgan Kaufmann, |c ©2005. | ||
| 300 | |a 1 online resource (1 volume) | ||
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| 490 | 1 | |a Morgan Kaufmann series in systems on silicon | |
| 500 | |a Includes index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. | |
| 520 | |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification | ||
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Application-specific integrated circuits. | |
| 650 | 0 | |a Field programmable gate arrays. | |
| 650 | 6 | |a Circuits intégrés à la demande. | |
| 650 | 6 | |a Réseaux logiques programmables par l'utilisateur. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 0 | 7 | |a Application specific integrated circuits. |2 cct |
| 650 | 7 | |a Field programmable gate arrays |2 fast | |
| 650 | 7 | |a Application-specific integrated circuits |2 fast | |
| 776 | 0 | 8 | |i Print version: |a Munden, Richard. |t ASIC and FPGA verification. |d San Francisco, Calif. : Morgan Kaufmann, ©2005 |z 0125105819 |w (OCoLC)56642597 |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
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