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System-on-a-chip : design and test /
Starting with a basic overview of system-on-a-chip (SoC), including definitions of related terms, this new book helps you understand SoC design challenges, and the latest design and test methodologies. You see how ASIC technology evolved to an embedded cores-based concept that includes pre-designed,...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Boston, MA :
Artech House,
2000.
|
| Colección: | Artech House signal processing library.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Rajsuman, Rochit. | |
| 245 | 1 | 0 | |a System-on-a-chip : |b design and test / |c Rochit Rajsuman. |
| 260 | |a Boston, MA : |b Artech House, |c 2000. | ||
| 300 | |a 1 online resource (xiii, 277 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
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| 490 | 1 | |a Artech House signal processing library | |
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Design -- Architecture of the present-day SoC -- Design issues of SoC -- Hardware-software codesign -- Codesign flow -- Codesign tools -- Core libraries, EDA tools, and web pointers -- Core libraries -- EDA tools and vendors -- Web pointers -- Design methodology for logic cores -- SoC design flow -- General guidelines for design reuse -- Synchronous design -- Memory of mixed-signal design -- On-chip buses -- Clock distribution -- Clear/set/reset signals -- Physical design -- Deliverable models -- Design process for soft and firm cores -- Design flow -- Development process for soft/firm cores -- RTL guidelines -- Soft/firm cores productization -- Design process for hard cores -- Unique design issues in hard cores -- Development process for hard cores -- Sign-off checklist and deliverables -- Sign-off checklist -- Soft core deliverables -- Hard core deliberables -- System integration -- Designing with hard cores -- Designing with soft cores -- System verification -- Design methodology for memory and analog cores -- Why large embeded memories -- Design methodology for embedded memories -- Circuit techniques -- Memory compiler -- Simulation models -- Specifications of analog circuits -- Analog-to-digital converter -- Phase-locked loops -- High-speech circuits -- Rambus ASIC cell -- IEEE 1394 serial bus (Firewire) PHY layer -- High-Speed I/O -- Design validation -- Core-level validation -- Core validation plan -- Testbenches -- Core-level timing verification -- Core interface verification -- Protocol verification -- Gate-level simulation -- SoC design validation -- Cosimulation -- Emulation -- Hardware prototypes -- Core and SoC design examples -- Microprocessor cores -- V830R/AV superscaler RISC core -- Design of powerPC 603e core -- Comments of memory core generation -- Core integration and on-chip bus -- Examples of SoC -- Media processors -- Testbility of set-top box SoC -- Testing of digital logic cores -- SoC test issues -- Access, control, and isolation -- IEEE P1500 effort -- Cores without boundary scan -- Core test language -- Core with boundary scan -- Core test and IP protection -- Test methodology for design reuse -- Guidelines for core testability -- High-level test synthesis -- Testing of microprocessor cores -- Built-in self-test method -- Examples: testability features of ARM processor core -- Debug support for microprocessor cores -- Testing of embedded memories -- Memory fault models and test algorithms -- Fault models -- Test algorithms -- Effectiveness of test algorithms -- Modification with multiple data background -- Modification for multiport memories -- Algorithm for double-buffered memories -- Test methods for embedded memories -- Testing through ASIC functional test -- Test application by direct access -- Test application by scan or collar register -- Memory built-in self-test -- Testing by on-chip microprocessor -- Summary of test methods for embedded memories -- Memory redundancy and repair -- Hard repair -- soft repair -- mError detection and correction codes -- Production testing of SoC with large embedded memory -- Testing of analog and mixed-signal cores -- Analog parameters and characterization -- Digital-to-analog converter -- Analog-to-digital converter -- Phase-locked loop -- Design-for-test and buil-in self-test methods for analog cores -- Fluence technology's analog BIST -- LogiVision's analog BIST -- Testing by on-chip microprocessor -- IEEE P1149.4 -- Testing of specific analog circuits -- Rambus ASIC cell -- Teting of 1394 serial bus/firewire -- Iddq testing -- Physical defects -- Bridging (shorts) -- Gate-oxide defects -- Open (breaks) -- Effectiveness of iddq testing -- Iddq testing difficulties in SoC -- Design-for-iddq-testing -- Iddq test vector generation -- Production testing -- Production test flow -- At-speed testing -- RTD and dead cycles -- Fly-by -- Speed binning -- Production throughput and materials handling -- Test logistics -- Tester setup -- Multi-DUT testing. | |
| 506 | |3 Use copy |f Restrictions unspecified |2 star |5 MiAaHDL | ||
| 533 | |a Electronic reproduction. |b [Place of publication not identified] : |c HathiTrust Digital Library, |d 2010. |5 MiAaHDL | ||
| 538 | |a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. |u http://purl.oclc.org/DLF/benchrepro0212 |5 MiAaHDL | ||
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| 520 | 3 | |a Starting with a basic overview of system-on-a-chip (SoC), including definitions of related terms, this new book helps you understand SoC design challenges, and the latest design and test methodologies. You see how ASIC technology evolved to an embedded cores-based concept that includes pre-designed, reusable Intellectual Property (IP) cores that act as microprocessors, data storage devices, DSP, bus control, and interfaces -- all "stitched" together by a User's Defined Logic (UDL). |c Publisher abstract | |
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 650 | 0 | |a Embedded computer systems |x Design and construction. | |
| 650 | 0 | |a Embedded computer systems |x Testing. | |
| 650 | 0 | |a Application-specific integrated circuits |x Design and construction. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 7 | |a Application-specific integrated circuits |x Design and construction. |2 fast |0 (OCoLC)fst00811723 | |
| 650 | 7 | |a Embedded computer systems |x Design and construction. |2 fast |0 (OCoLC)fst00908300 | |
| 650 | 7 | |a Embedded computer systems |x Testing. |2 fast |0 (OCoLC)fst00908304 | |
| 650 | 7 | |a System-on-Chip |2 gnd | |
| 650 | 7 | |a Systèmes enfouis (informatique) |x Conception et construction. |2 ram | |
| 650 | 7 | |a Systèmes enfouis (informatique) |x Essais. |2 ram | |
| 650 | 7 | |a Circuits intégrés à la demande |x Conception et construction. |2 ram | |
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| 653 | |a Electrotechnique | ||
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