Layout techniques for integrated circuit designers /

This book provides complete step-by-step guidance on the physical implementation of modern integrated circuits, showing you their limitations and guiding you through their common remedies. The book describes today's manufacturing techniques and how they impact design rules. You will understand...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Sahrling, Mikael, 1964- (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: [Place of publication not identified] : Artech House, 2022.
Temas:
Integrated circuit layout.
Circuits intégrés > Implantation.
Integrated circuit layout
Integrated Circuits
Technology & Engineering
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Intro
  • Layout Techniques for Integrated Circuit Designers
  • Contents
  • Preface
  • Chapter 1 Introduction
  • Part I: Manufacturing and Physical Layout Techniques
  • Chapter 2 Preliminaries
  • 2.1 Silicon Manufacturing Basics
  • 2.1.1 Basic Overview
  • 2.1.2 Epitaxy
  • 2.1.3 Oxidation
  • 2.1.4 Photolithography
  • 2.1.5 Etching
  • 2.1.6 Doping
  • 2.1.7 Deposition
  • 2.1.8 Planarization
  • 2.1.9 Wafer Stack-Up
  • 2.1.10 Thinning
  • 2.1.11 Singulation (Dicing/Cutting)
  • 2.1.12 Bonding
  • 2.1.13 Bumping
  • 2.1.14 Packaging
  • 2.1.15 Wafer-Level Probe Test
  • 2.1.16 Final Test
  • 2.2 Semiconductor Yield
  • 2.2.1 Functional Yield
  • 2.2.2 Parametric Yield
  • 2.3 Layout Database Formats
  • 2.3.1 Calma and GDSII
  • 2.3.2 OASIS and Open Access
  • 2.4 Schematic Netlist Formats
  • 2.4.1 SPICE Format
  • 2.4.2 CDL Format
  • 2.4.3 Spectre Format
  • 2.5 Simulation Output Formats
  • 2.6 Formats Used in the Book
  • 2.7 Summary
  • Exercises
  • References
  • Chapter 3 Device Formation in Layout
  • 3.1 Process Stack-Up
  • 3.2 Fundamental Devices
  • 3.2.1 Silicide Formation
  • 3.2.2 Resistors
  • 3.2.3 Maxwell's Equations
  • 3.2.4 Capacitors
  • 3.2.5 Inductors
  • 3.2.6 Transmission Lines
  • 3.2.7 MOSFET Devices
  • 3.2.8 Bipolar Transistor Devices
  • 3.2.9 Summary of Device Manufacturing
  • 3.3 Device Matching
  • 3.3.1 Process-Related Causes of Mismatch
  • 3.3.2 Layout Strategies to Minimize Mismatch
  • 3.3.3 Design Strategies to Reduce the Effect of Mismatch
  • 3.4 Manufacturing Challenges: Design Rules
  • 3.4.1 Design Rule Derivations
  • 3.4.2 Width Rules
  • 3.4.3 Spacing Rules
  • 3.4.4 Enclosure/Overlap Rules
  • 3.4.5 Area Rules
  • 3.4.6 Antenna Rules
  • 3.4.7 Density Rules
  • 3.5 Future Directions
  • 3.6 Summary
  • Exercises
  • References
  • Chapter 4 Layout with Ultrasmall Geometry CMOS Technologies
  • 4.1 Small Geometry Effects
  • 4.1.1 Thin Metal Effects
  • 4.1.2 Strain Effects
  • 4.1.3 Well Proximity Effect
  • 4.1.4 Substrate Contact Distance Requirements
  • 4.1.5 EM and IR Drop
  • 4.2 Small Geometry CMOS Flow
  • 4.2.1 Strategies to Manage High-Resistance Interconnect
  • 4.2.2 Strategies to Manage Parasitic Capacitance
  • 4.2.3 Strategies to Manage Parasitic Inductance
  • 4.2.4 Overall Parasitic Strategies
  • 4.3 Summary
  • Exercises
  • References
  • Chapter 5 Layout with Bipolar Technologies SiGe
  • 5.1 Introduction
  • 5.2 Process Flow
  • 5.2.1 Physics of SiGe Bipolar Transistors
  • 5.2.2 Collector Formation
  • 5.2.3 Base Formation
  • 5.2.4 Emitter Formation
  • 5.2.5 Parasitics of Bipolar Transistors
  • 5.2.6 PNP Transistors
  • 5.2.7 Future Direction of SiGe transistors
  • 5.3 Layout Flow
  • 5.3.1 SIGe Technology Metallization
  • 5.3.2 Transistor Layout Topologies
  • 5.4 Other Technologies
  • 5.4.1 InP HBT
  • 5.4.2 GaAs HBT
  • 5.4.3 Comparison of Different HBT Technologies
  • 5.5 Summary
  • References
  • Chapter 6 Aspects of High-Speed Layout 10-100+ GHz
  • 6.1 Single-Ended Transmission Lines On-Chip

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