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Multi-processor system-on-chip. 1, Architectures /
A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes - Architectures and Applications - therefore celebrates the 20th anniversary of MPSoC...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London : Hoboken :
ISTE, Ltd. ; Wiley,
2021.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000 a 4500 | ||
|---|---|---|---|
| 001 | EBOOKCENTRAL_on1243532832 | ||
| 003 | OCoLC | ||
| 005 | 20240329122006.0 | ||
| 006 | m o d | ||
| 007 | cr un|---aucuu | ||
| 008 | 210327s2021 enk o 000 0 eng d | ||
| 040 | |a EBLCP |b eng |e pn |c EBLCP |d DG1 |d OCLCO |d YDX |d UKAHL |d OCLCF |d OCLCQ |d OCLCO |d OCLCQ |d UPM |d OCLCQ |d OCLCO |d WSU |d OCLCL | ||
| 019 | |a 1242577731 | ||
| 020 | |a 9781119818298 |q (electronic bk. ; |q oBook) | ||
| 020 | |a 111981829X |q (electronic bk. ; |q oBook) | ||
| 020 | |a 9781119818274 | ||
| 020 | |a 1119818273 | ||
| 020 | |z 9781789450217 | ||
| 020 | |z 1789450217 | ||
| 029 | 1 | |a AU@ |b 000069138768 | |
| 035 | |a (OCoLC)1243532832 |z (OCoLC)1242577731 | ||
| 050 | 4 | |a TK7895.E42 | |
| 082 | 0 | 4 | |a 006.2/2 |2 23 |
| 049 | |a UAMI | ||
| 245 | 0 | 0 | |a Multi-processor system-on-chip. |n 1, |p Architectures / |c coordinated by Liliana Andrade, Frédéric Rousseau. |
| 246 | 3 | 0 | |a Architectures |
| 260 | |a London : |b ISTE, Ltd. ; |a Hoboken : |b Wiley, |c 2021. | ||
| 300 | |a 1 online resource (321 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Cover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Foreword -- Acknowledgments -- PART 1: Processors -- 1 Processors for the Internet of Things -- 1.1. Introduction -- 1.2. Versatile processors for low-power IoT edge devices -- 1.2.1. Control processing, DSP and machine learning -- 1.2.2. Configurability and extensibility -- 1.3. Machine learning inference -- 1.3.1. Requirements for low/mid-end machine learning inference -- 1.3.2. Processor capabilities for low-power machine learning inference -- 1.3.3. A software library for machine learning inference | |
| 505 | 8 | |a 1.3.4. Example machine learning applications and benchmarks -- 1.4. Conclusion -- 1.5. References -- 2 A Qualitative Approach to Many-core Architecture -- 2.1. Introduction -- 2.2. Motivations and context -- 2.2.1. Many-core processors -- 2.2.2. Machine learning inference -- 2.2.3. Application requirements -- 2.3. The MPPA3 many-core processor -- 2.3.1. Global architecture -- 2.3.2. Compute cluster -- 2.3.3. VLIW core -- 2.3.4. Coprocessor -- 2.4. The MPPA3 software environments -- 2.4.1. High-performance computing -- 2.4.2. KaNN code generator -- 2.4.3. High-integrity computing | |
| 505 | 8 | |a 2.5. Conclusion -- 2.6. References -- 3 The Plural Many-core Architecture -- High Performance at Low Power -- 3.1. Introduction -- 3.2. Related works -- 3.3. Plural many-core architecture -- 3.4. Plural programming model -- 3.5. Plural hardware scheduler/synchronizer -- 3.6. Plural networks-on-chip -- 3.6.1. Scheduler NoC -- 3.6.2. Shared memory NoC -- 3.7. Hardware and software accelerators for the Plural architecture -- 3.8. Plural system software -- 3.9. Plural software development tools -- 3.10. Matrix multiplication algorithm on the Plural architecture | |
| 505 | 8 | |a 4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs -- 4.1. Introduction -- 4.2. Related works -- 4.3. ASIP architecture -- 4.4. Single-core scaling -- 4.5. MPSoC overview -- 4.6. NoC parameter exploration -- 4.7. Summary and conclusion -- 4.8. References -- PART 2: Memory -- 5 Tackling the MPSoC DataLocality Challenge -- 5.1. Motivation -- 5.2. MPSoC target platform -- 5.3. Related work -- 5.4. Coherence-on-demand: region-based cache coherence -- 5.4.1. RBCC versus global coherence -- 5.4.2. OS extensions for coherence-on-demand -- 5.4.3. Coherency region manager | |
| 505 | 8 | |a 5.4.4. Experimental evaluations -- 5.4.5. RBCC and data placement -- 5.5. Near-memory acceleration -- 5.5.1. Near-memory synchronization accelerator -- 5.5.2. Near-memory queue management accelerator -- 5.5.3. Near-memory graph copy accelerator -- 5.5.4. Near-cache accelerator -- 5.6. The big picture -- 5.7. Conclusion -- 5.8. Acknowledgments -- 5.9. References -- 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture -- 6.1. Introduction -- 6.2. MAGIC NOR gate -- 6.3. In-memory algorithms for latency reduction -- 6.4. Synthesis and in-memory mapping methods | |
| 500 | |a 6.4.1. SIMPLE. | ||
| 520 | |a A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes - Architectures and Applications - therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. | ||
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Systems on a chip. | |
| 650 | 0 | |a Multiprocessors. | |
| 650 | 6 | |a Systèmes sur une puce. | |
| 650 | 6 | |a Multiprocesseurs. | |
| 650 | 7 | |a Multiprocessors |2 fast | |
| 650 | 7 | |a Systems on a chip |2 fast | |
| 700 | 1 | |a Andrade, Liliana. | |
| 700 | 1 | |a Rousseau, Frédéric, |d 1967- |1 https://id.oclc.org/worldcat/entity/E39PCjwJWHpywWjBBg84w9rQbd | |
| 758 | |i has work: |a Multi-processor system-on-chip Architectures 1 (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGyjr66rjYJX6qQBwKf6rq |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Andrade, Liliana. |t Multi-Processor System-On-Chip 1. |d Newark : John Wiley & Sons, Incorporated, ©2021 |z 9781789450217 |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=6523042 |z Texto completo |
| 938 | |a Askews and Holts Library Services |b ASKH |n AH38415504 | ||
| 938 | |a ProQuest Ebook Central |b EBLB |n EBL6523042 | ||
| 938 | |a YBP Library Services |b YANK |n 302001920 | ||
| 994 | |a 92 |b IZTAP | ||