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Birthing the computer : from drums to cores /
Birthing the Computer: From Drums to Cores examines the evolution of computer systems architecture based on two evolutionary developments: memory technology - magnetic drums to magnetic cores - and CPU technology - transistors. This evolution, exemplified by a number of academic and commercial compu...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Newcastle-upon-Tyne :
Cambridge Scholars Publishing,
2017.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Kaisler, Stephen H. |q (Stephen Hendrick), |e author. |1 https://id.oclc.org/worldcat/entity/E39PCjKPjBVVCvdjcMgVDjWcHd | |
| 245 | 1 | 0 | |a Birthing the computer : |b from drums to cores / |c by Stephen H. Kaisler. |
| 264 | 1 | |a Newcastle-upon-Tyne : |b Cambridge Scholars Publishing, |c 2017. | |
| 300 | |a 1 online resource (369 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
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| 505 | 0 | |a Table of Contents; List of Figures; List of Tables; Acknowledgement; Introduction; Part I: Magnetic Drum Machines; Chapter One; 1.1 650 System Architecture; 1.1.1 Magnetic Drum Memory; 1.1.2 Arithmetic Unit; 1.1.3 IBM 650 Self-Checking; 1.1.4 IBM 650 Console; 1.1.5 Magnetic Tape Units; 1.1.6 IBM 652 Control Unit; 1.1.7 IBM 653 High-Speed Core Storage Unit; 1.1.8 IBM 407 Accounting Machine; 1.2 IBM 650 Instruction Set; 1.2.1 I/O Instructions; 1.2.2 Arithmetic Instructions; 1.2.3 Shifting Instructions; 1.2.4 Branching Instructions; 1.2.5 Table Lookup Instruction | |
| 505 | 8 | |a 1.2.6 Miscellaneous Instructions1.2.7 Index Accumulator Instructions; 1.2.8 Index Accumulator Operations Instructions; 1.2.9 Floating Point Instructions; 1.2.10 IAS Instruction; 1.3 IBM 650 Programming; 1.4 Symbolic Assembly; 1.5 IBM 650 RAMAC; 1.6 IBM 650 Assessment; Chapter Two; 2.1 LGP-30 System Architecture; 2.2 LGP-30 Instruction Set; 2.3 The Story of Mel; 2.4 LGP-30 Assessment; 2.5 The LGP-21; 2.5.1 LGP-21 System; 2.5.2 LGP-21 Memory; 2.5.3 LGP-21 Control Registers; 2.6 LGP-21 Instruction Set; 2.7 Timing and Optimization; 2.8 LGP-21 Assessment; Chapter Three; 3.1 Bendix G-15 | |
| 505 | 8 | |a 3.2 G-15 System Configuration3.2.1 Short Lines; 3.2.2 Registers; 3.2.3 Command Lines; 3.2.4 I/O System; 3.3 G-15 Instruction Set; 3.3.1 Special Values for S/D Fields; 3.3.2 Special Instructions; 3.4 Peripheral Devices; 3.4.1 Magnetic Tape MTA-2; 3.4.2 Digital Differential Analyzer DA-1; 3.4.3 Graph Plotter PA-3; 3.4.4 Punched Card Coupler CA-1/CA-2; 3.4.5 Universal Code Accessory AN-1; 3.5 Programming Languages; 3.5.1 ALGO; 3.5.2 Intercom 1000; 3.5.3 Sample G-15 Program; 3.6 Tracking Station Application; 3.7 G-15 Assessment; Further Reading; Exercises for the Reader | |
| 505 | 8 | |a Part II: Core Memory MachinesChapter Four; 4.1 BIZMAC System Architecture; 4.2 BIZMAC I/O System; 4.3 Data Representation; 4.4 BIZMAC Instruction Set; 4.5 BIZMAC Assessment; Chapter Five; 5.1 Atlas System Architecture; 5.1.1 Central Processor; 5.1.2 Program Control; 5.1.3 Storage Hierarchy; 5.1.4 Virtual Storage; 5.2 Peripherals; 5.3 Atlas Instruction Set; 5.3.1 Floating Point Arithmetic Instructions; 5.3.2 Indexing Operations; 5.3.3 Atlas Branching Instructions; 5.3.4 Atlas Shifting Instructions; 5.3.5 Atlas Odd/Even test Instructions; 5.3.6 Atlas B-test Register Instructions | |
| 505 | 8 | |a 5.3.7 Atlas Instruction Example5.4 Atlas Programming; 5.5 The Atlas Supervisor; 5.5.1 Structure of the Atlas Supervisor; 5.5.2 Job Structure; 5.5.3 Programs; 5.5.4 Process Control; 5.5.5 Interrupt Handling; 5.5.6 Atlas Supervisor Assessment; 5.6 Atlas 2; 5.6.1 Atlas 2 Central Processor; 5.6.2 Atlas 2 Memory; 5.6.3 Magnetic Tape; 5.6.4 Magnetic Disc Files; 5.7 The Atlas 2 Supervisor; 5.7.1 Interrupt Routines; 5.7.2 Supervisor Extracode Routines; 5.7.3 Extended Interrupt Routines; 5.7.4 Object Programs; 5.7.5 Error Conditions; 5.8 Atlas Assessment; Chapter Six; 6.1 JOHNNIAC System Architecture | |
| 520 | |a Birthing the Computer: From Drums to Cores examines the evolution of computer systems architecture based on two evolutionary developments: memory technology - magnetic drums to magnetic cores - and CPU technology - transistors. This evolution, exemplified by a number of academic and commercial computing machines, yielded significant performance improvements and more storage leading to more effective utilization. These features would drive the development of programming languages and system software that would enhance the usability of the machines to solve more complex problems in both business. | ||
| 504 | |a Includes bibliographical references (pages [332]-339) and index. | ||
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 650 | 0 | |a Computer architecture |x History. | |
| 650 | 6 | |a Ordinateurs |x Architecture |x Histoire. | |
| 650 | 7 | |a Mainframes & minicomputers. |2 bicssc | |
| 650 | 7 | |a Electronics engineering. |2 bicssc | |
| 650 | 7 | |a History of science. |2 bicssc | |
| 650 | 7 | |a COMPUTERS |x Computer Literacy. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Computer Science. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Data Processing. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Hardware |x General. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Information Technology. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Machine Theory. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Reference. |2 bisacsh | |
| 650 | 7 | |a Computer architecture |2 fast | |
| 655 | 7 | |a History |2 fast | |
| 758 | |i has work: |a Birthing the computer (Text) |1 https://id.oclc.org/worldcat/entity/E39PCG7FF67fdbyPy4Cvd3gYfq |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=4884279 |z Texto completo |
| 938 | |a eLibro |b ELBO |n ELB152340 | ||
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