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Digital Integrated Circuits : Analysis and Design, Second Edition /
"Exponential improvement in functionality and performance of digital integrated circuits has revolutionized the way we live and work. The continued scaling down of MOS transistors has broadened the scope of use for circuit technology to the point that texts on the topic are generally lacking af...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Boca Raton, FL :
CRC Press,
2011.
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| Edición: | Second edition. |
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Introduction Historical Perspective and Moore's Law Electrical Properties of Digital Integrated Circuits Computer-Aided Design and Verification Fabrication Semiconductors and Junctions The MOS Transistor MOS Gate Circuits Interconnect Dynamic CMOS Low-Power CMOS Bistable Circuits Memories Input/Output and Interface Circuits Fabrication Basic CMOS Fabrication Sequence Advanced Processing for High-Performance CMOS Lithography and Masks Layout and Design Rules Testing and Yield Packaging Burn-In and Accelerated Testing Semiconductors and p-n Junctions Crystal Structure of Silicon Energy Bands Carrier Concentrations Current Transport Carrier Continuity Equations Poisson's Equation The p-n Junction Metal-Semiconductor
- Junctions SPICE Models The MOS Transistor The MOS Capacitor Threshold Voltage MOSFET Current-Voltage Characteristics Short-Channel MOSFETs MOSFET Design MOSFET Capacitances MOSFET Constant-Field Scaling SPICE MOSFET Models SPICE Demonstrations MOS Gate Circuits Inverter Static Characteristics Critical Voltages Dissipation Propagation Delays Fan-Out NOR Circuits NAND Circuits Exclusive OR (XOR) Circuit General Logic Design Pass Transistor Circuits SPICE Demonstrations Static CMOS Voltage Transfer Characteristic Load Surface Analysis Critical Voltages Crossover (Short-Circuit) Current Propagation Delays Inverter Rise and Fall Times Propagation Delays in Short-Channel CMOS Power
- Dissipation Fan-Out Circuit Delays as Functions of Fan-Out CMOS Ring Oscillator CMOS Inverter Design CMOS NAND Circuits CMOS NOR Circuits Other Logic Functions in CMOS 74HC Series CMOS Pseudo NMOS Circuits Scaling of CMOS Latch-Up in CMOS SPICE Demonstrations Interconnect Capacitance of Interconnect Resistance of Interconnect Inductance of Interconnect Modeling Interconnect Delays Crosstalk Polysilicon Interconnect SPICE Demonstrations Practical Perspective Dynamic CMOS Rise Time Fall Time Charge Sharing Charge Retention Logic Design Alternative Form Using a p-MOS Pull-Up Network Cascading of Dynamic Logic Circuits Domino Logic Multiple-Output Domino Logic Zipper Logic Dynamic Pass Transistor Circuits CMOS
- Transmission Gate Circuits SPICE Demonstrations Practical Perspective Low-Power CMOS Low-Voltage CMOS Multiple Voltage CMOS Dynamic Voltage Scaling Active Body Biasing Multiple-Threshold CMOS Adiabatic Logic Silicon-on-Insulator Practical Perspective Bistable Circuits Set-Reset Latch SR Flip-flop JK Flip-flops Other Flip-flops Schmitt Triggers SPICE Demonstrations Practical Perspective Digital Memories Static Random Access Memory Dynamic Random Access Memory Read-Only Memory Programmable Read-Only Memory Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory Flash Memory Other Nonvolatile Memories Access Times in Digital Memories Row and Column Decoder
- Design Practical Perspective Input/Output and Interface Circuits Input Electrostatic Discharge Protection Input Enable Circuits CMOS Output Buffers Tri-State Outputs Interface Circuits SPICE Demonstrations Appendices
- Cover; Half Title; Title Page; Copyright Page; Dedication; Table of Contents; About the Author; Preface; 1: Introduction; 1.1 Historical Perspective and Moore's Law; 1.2 Electrical Properties of Digital Integrated Circuits; 1.2.1 Logic Function; 1.2.2 Static Voltage Transfer Characteristics; 1.2.3 Transient Characteristics; 1.2.4 Fan-In and Fan-Out; 1.2.5 Dissipation; 1.2.6 Power Delay Product; 1.3 Computer-Aided Design and Verifi cation; 1.4 Fabrication; 1.5 Semiconductors and Junctions; 1.6 The MOS Transistor; 1.7 MOS Gate Circuits; 1.8 Interconnect; 1.9 Dynamic CMOS; 1.10 Low-Power CMOS
- 1.11 Bistable Circuits1.12 Memories; 1.13 Input/Output and Interface Circuits; 1.14 Practical Perspective; 1.15 Summary; 1.16 Exercises; References; 2: Fabrication; 2.1 Introduction; 2.2 Basic CMOS Fabrication Sequence; 2.3 Advanced Processing for High-Performance CMOS; 2.3.1 Copper Metal; 2.3.2 Metal Gates; 2.3.3 High-k Gate Dielectric; 2.4 Lithography and Masks; 2.5 Layout and Design Rules; 2.5.1 Minimum Line Widths and Spacings; 2.5.2 Contacts and Vias; 2.6 Testing and Yield; 2.7 Packaging; 2.8 Burn-In and Accelerated Testing; 2.9 Practical Perspective; 2.10 Summary; 2.11 Exercises
- 3.9 Metal-Semiconductor Junctions3.10 SPICE Models; 3.11 Practical Perspective; 3.12 Summary; 3.13 Exercises; References; 4: The MOS Transistor; 4.1 Introduction; 4.2 The MOS Capacitor; 4.3 Threshold Voltage; 4.4 MOSFET Current-Voltage Characteristics; 4.4.1 Linear Operation; 4.4.2 Saturation Operation; 4.4.3 Subthreshold Operation; 4.4.4 Transit Time; 4.5 Short-Channel MOSFETs; 4.5.1 The Short-Channel Effect; 4.5.2 Narrow-Channel Effect; 4.5.3 Drain-Induced Barrier Lowering; 4.5.4 Channel Length Modulation; 4.5.5 Field-Dependent Mobility and Velocity Saturation
- 4.5.6 Transit Time in Short-Channel MOSFETs4.6 MOSFET Design; 4.7 MOSFET Capacitances; 4.7.1 Oxide Capacitances; 4.7.2 p-n Junction Capacitances; 4.7.3 The Miller Effect; 4.8 MOSFET Constant-Field Scaling; 4.9 SPICE MOSFET Models; 4.9.1 MOSFET Level 1 Model; 4.9.2 Berkeley Short-Channel Insulated Gate Field Effect Transistor Model; 4.9.2.1 BSIM1 Parameters; 4.9.2.2 BSIM1 Threshold Voltage; 4.9.2.3 BSIM1 Drain Current-Linear Region; 4.9.2.4 BSIM1 Drain Current-Saturation Region; 4.9.2.5 BSIM1 Drain Current-Subthreshold Region; 4.9.2.6 Hand Calculations Related to the BSIM1