Nanoelectronics : Materials, Devices, Applications, 2 Volumes.

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Puers, Robert
Otros Autores: Baldi, Livio, Van de Voorde, Marcel, Van Nooten, Sebastiaan E.
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Newark : John Wiley & Sons, Incorporated, 2017.
Colección:Applications of Nanotechnology Ser.
Temas:
Nanoelectronics.
Nanoélectronique.
Nanoelectronics
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Nanoelectronics: Materials, Devices, Applications
  • Series Editor Preface
  • About the Series Editor
  • Contents
  • Foreword
  • 1 The Nanoelectronics Industry
  • 2 The Nanoelectronics Ecosystem
  • 3 Miniaturization
  • 4 Functional Diversification
  • 5 Embedding Software
  • 6 Restructuring the Value Chain
  • 6.1 Value Chain Fragmentation
  • 6.2 Vertical Integration
  • 6.3 Emerging Value Chain
  • 7 Opportunities and Perspectives
  • 7.1 Emerging Market Opportunities
  • Nanoelectronics for Digital Agenda
  • Electronics on the EU's Political Agenda
  • 1 Digital Action in the European Union
  • 2 A Focus on Micro- and Nanoelectronics
  • 3 Difficult Times Ahead
  • 4 Why the Electronics Sector Matters
  • 5 Europe Has a Chance
  • 6 Industrial Strategy for Micro- and Nanoelectronics in Europe
  • 7 Pooling Resources for Research and Development
  • 8 Getting Industry to Act
  • 9 State Aid or No State Aid?
  • 10 The EU Cannot Give Aid But It Can Help
  • 11 What Next? The EU Investment Plan
  • Preface
  • Part One: Fundamentals on Nanoelectronics
  • 1: A Brief History of the Semiconductor Industry
  • 1.1 From Microelectronics to Nanoelectronics and Beyond
  • 1.1.1 You Got to Have Science, Genius!
  • 1.1.2 What Would Science Be Without Technology?
  • 1.1.3 The Magic of Economics
  • 1.1.4 Back to the MOS
  • 1.1.5 Technology Innovation Must Go On!
  • 1.1.6 Bipolar against MOS!
  • 1.1.7 Finally It All Comes Together
  • 1.2 The Growth of the Semiconductor Industry: An Eyewitness Report
  • 1.2.1 The Making of the PC Industry
  • 1.2.2 The DRAM Wars
  • 1.2.3 The Introduction of New Materials
  • 1.2.4 Microprocessors Introduction Cycle Goes from 4 to 2 Year
  • 1.2.5 The 300 mm Wafer Size Conversion
  • 1.2.6 The 1990s: Scaling, Scaling, Scaling
  • 1.2.7 Equivalent Scaling: Designers Will Never Know What We Have Done.
  • 1.2.8 Is There Life Beyond the Limits of CMOS and of Von Neumann Architecture?
  • 1.2.9 Nanoelectronics to the Rescue
  • 1.2.10 The New Manhattan Project
  • 1.2.11 System Requirements and Heterogeneous Integration
  • 1.2.12 Evolve or Become Irrelevant
  • 1.2.13 Bringing It all Together
  • Acknowledgments
  • 2: More-than-Moore Technologies and Applications
  • 2.1 Introduction
  • 2.2 ``More Moore ́́and ``More-than-Moore ́́
  • 2.3 From Applications to Technology
  • 2.4 More-than-Moore Devices
  • 2.4.1 Interacting with the Outside World
  • 2.4.2 Powering
  • 2.4.3 More-than-Moore Technologies
  • 2.5 Application Domains
  • 2.5.1 Automotive
  • 2.5.2 Health Care
  • 2.5.2.1 Wearable Health Care
  • 2.5.2.2 Biochips and Lab-on-Chips
  • 2.5.3 Safety and Security
  • 2.5.4 Industrial Applications
  • 2.5.4.1 Integrated Power
  • 2.5.4.2 Lighting
  • 2.6 Conclusions
  • Acknowledgement
  • References
  • 3: Logic Devices Challenges and Opportunities in the Nano Era
  • 3.1 Introduction: Dennard's Scaling and Moore's Law Trends and Limits
  • 3.2 Power Performance Trade-Off for 10 nm, 7 nm, and Below
  • 3.2.1 Electrostatics of Advanced CMOS Devices
  • 3.2.2 Speed Performance Metrics of CMOS Technologies
  • 3.2.2.1 Switching Delay Formulation
  • 3.2.2.2 Effective Current and MOSFET Electrostatics
  • 3.2.3 Parasitics Capacitance in Logic Devices
  • 3.2.3.1 Effective Capacitance of an Inverter Switch
  • 3.2.3.2 Parasitic Capacitance Calculation Method
  • 3.2.4 Power Dissipation in Transistor Devices
  • 3.2.4.1 Static Power Dissipation
  • 3.2.4.2 Dynamic Power Dissipation
  • 3.2.4.3 Limitation of the Minimum Voltage Supply: The Vth Variability
  • 3.2.5 Summary of the Key Points of CMOS Devices
  • 3.3 Device Structures and Materials in Advanced CMOS Nodes
  • 3.3.1 SCE Immune MOSFET Architectures
  • 3.3.1.1 Fully Depleted SOI, UTB, and UTBB Structures.
  • 3.3.1.2 FinFET and Double-Gate Devices
  • 3.3.1.3 Gate-All-Around Transistors and Nanowires
  • 3.3.2 Parasitic Capacitances in Advanced Device Structures
  • 3.3.3 High-Mobility Materials and Devices
  • 3.3.3.1 Transistor Current in Ultrashort Devices
  • 3.3.3.2 Material Engineering for Transport Enhancement
  • 3.3.3.3 Choice of Materials for Advanced CMOS
  • References
  • 4: Memory Technologies
  • 4.1 Introduction
  • 4.2 Mainstream Memories (DRAM and NAND): Evolution and Scaling Limits
  • 4.3 Emerging Memories Technologies
  • 4.3.1 Ferroelectric Memories
  • 4.3.2 Magnetic Memories
  • 4.3.3 Phase Change Memories
  • 4.3.4 Resistive RAMs: OxRAM and CBRAM
  • 4.3.5 Other Memory Concepts
  • 4.4 Emerging Memories Architectures
  • 4.4.1 From Cell to Arrays
  • 4.4.2 3D RRAM Architectures
  • 4.5 Opportunities for Emerging Memories
  • 4.5.1 Storage Class Memory
  • 4.5.2 Embedded Memories
  • 4.6 Conclusions
  • References
  • Part Two: Devices in the Nano Era
  • 5: Beyond-CMOS Low-Power Devices: Steep-Slope Switches for Computation and Sensing
  • 5.1 Digital Computing in Post-Dennard Nanoelectronics Era
  • 5.2 Beyond CMOS Steep-Slope Switches
  • 5.3 Convergence of Requirements for Energy-Efficient Computing and Sensing Technologies: Enabling Smart Autonomous Systems for IoE
  • 5.4 Conclusions and Perspectives
  • References
  • 6: RF CMOS
  • 6.1 Introduction
  • 6.2 Toward 5G and Beyond
  • 6.3 CMOS @ Millimeter-Wave: Challenges and Opportunities
  • 6.4 Terahertz in CMOS
  • 6.5 Conclusions
  • References
  • 7: Smart Power Devices Nanotechnology
  • 7.1 Introduction
  • 7.2 Si Power Devices
  • 7.2.1 Discrete versus Integrated Power Devices
  • 7.2.2 Low-Voltage MOSFETs
  • 7.2.3 High-Voltage MOSFETs
  • 7.2.4 IGBTs
  • 7.2.5 Device versus Application Landscape
  • 7.3 SiC Power Semiconductor Devices
  • 7.3.1 High-Voltage Blocking
  • 7.3.2 SiC Diodes/Rectifiers.
  • 7.3.3 Switch Devices
  • 7.3.4 JFETs and MOSFETs
  • 7.3.5 Bipolar Junction Transistors
  • 7.3.6 Ultrahigh Voltage-High-Injection Devices
  • 7.3.7 Concluding Remarks and Issues of Concerns for SiC Power Devices
  • 7.4 Power GaN Device Technology
  • 7.4.1 GaN Material and Device Physics
  • 7.4.2 Device Architectures
  • 7.4.2.1 HEMT (Schottky)
  • 7.4.2.2 MISHEMT
  • 7.4.2.3 Vertical Devices
  • 7.4.3 Ohmic Contacts
  • 7.4.4 E-MODE Devices
  • 7.4.4.1 Thin AlGaN Gate Barrier
  • 7.4.4.2 Charge Incorporation
  • 7.4.4.3 P-GaN or P-AlGaN Gate Structure
  • 7.4.4.4 HEMT/FET Hybrid
  • 7.4.4.5 Cascode
  • 7.4.5 Breakdown Voltage Engineering and Limitations
  • 7.4.5.1 Buffer Engineering
  • 7.4.5.2 Substrate Implantation
  • 7.4.5.3 Substrate Removal
  • 7.4.6 Dispersion Phenomena
  • 7.4.6.1 Surface-Induced Dispersion
  • 7.4.6.2 Buffer-Induced Dispersion
  • 7.4.7 Conclusion
  • 7.5 New Materials and Substrates for WBG Power Devices
  • References
  • 8: Integrated Sensors and Actuators: Their Nano-Enabled Evolution into the Twenty-First Century
  • 8.1 Introduction
  • 8.2 Sensors
  • 8.2.1 Mechanical Sensors
  • 8.2.1.1 Pressure Sensors and Microphones
  • 8.2.1.2 Gyroscopes and Accelerometers
  • 8.2.1.3 Resonators
  • 8.2.2 Vision/IR
  • 8.2.3 Terahertz (Thz) Imaging
  • 8.2.4 Radar/Lidar
  • 8.2.5 Gas Sensors
  • 8.2.6 Biosensors
  • 8.3 Actuators
  • 8.3.1 Electrostatic, Electromagnetic, and Piezoelectric
  • 8.3.2 Pneumatic, Phase Change, and Thermal Actuators
  • 8.3.3 Artificial Muscles
  • 8.4 Molecular Motors
  • 8.5 Transducer Integration and Connectivity
  • 8.6 Conclusion
  • References
  • Part Three: Advanced Materials and Materials Combinations
  • 9: Silicon Wafers as a Foundation for Growth
  • 9.1 Introduction
  • 9.2 Si Availability and Technologies to Produce Hyperpure Silicon in Large Quantities
  • 9.2.1 Metallurgical Silicon Production.
  • 9.2.2 Purification of Metallurgical Silicon via Trichlorosilane
  • 9.2.3 Production of Electronic Grade Polysilicon
  • 9.2.4 Monocrystalline Silicon Production
  • 9.2.4.1 CZ Growth Method
  • 9.2.4.2 FZ Growth Method
  • 9.2.5 Process Sequence of Silicon Wafer Production
  • 9.2.5.1 Mechanical Treatment
  • 9.2.5.2 Chemical Treatment
  • 9.2.5.3 Chemical-Mechanical Polishing
  • 9.2.5.4 Final Cleaning and Packaging
  • 9.2.5.5 Epitaxy
  • 9.3 The Exceptional Physical and Technological Properties of Monocrystalline Silicon for Device Manufacturing
  • 9.3.1 Doping
  • 9.3.2 Crystal Structure
  • 9.3.3 Silicon Dioxide
  • 9.3.4 Intrinsic Defect Categories
  • 9.3.5 Defect Kinetic Behavior
  • 9.4 Silicon and New Materials
  • 9.5 Example of Actual Advanced 300 mm Wafer Specification for Key Parameters
  • Acknowledgments
  • References
  • 10: Nanoanalysis
  • 10.1 Three-Dimensional Analysis
  • 10.1.1 X-Ray Tomography for the Analysis of TSV
  • 10.1.2 Progress in Atom Probe Tomography for Semiconductor Analysis
  • 10.2 Strain Analysis
  • 10.2.1 State-of-the-Art Strain Analysis by Precession Electron Diffraction
  • 10.2.2 X-Ray for Strain Measurements
  • 10.3 Compositional and Chemical Analysis
  • 10.3.1 Advanced Characterization of HKMG Stacks for Sub-14 nm Technology Nodes
  • 10.3.2 TEM Composition Analysis of NMOS Device
  • 10.4 Conclusions
  • Glossary
  • Acknowledgments
  • References
  • Part Four: Semiconductor Smart Manufacturing
  • 11. Front-End Processes
  • 11.1 A Standard MOS FEOL Process Flow
  • 11.2 Cleaning
  • 11.2.1 Wet Cleaning
  • 11.2.2 Advanced Aqueous Cleaning
  • 11.2.3 Nonaqueous Advanced Cleaning Approaches
  • 11.2.4 Advanced Drying Techniques
  • 11.3 Silicon Oxidation
  • 11.4 Doping and Dopant Activation
  • 11.4.1 Coimplantation
  • 11.4.2 Defect Engineering and Surface Treatment.

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