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Demystifying Chipmaking.
This book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the engineers who solved so...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Burlington :
Elsevier Science,
2005.
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| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Front Cover; Disclaimer ; Demystifying Chipmaking; Copyright Page; Contents; Foreword ; Acknowldgments ; About the Authors; What's on the CD-ROM?; Chapter 1. IC Fabrication Overview; Section 1. Introduction; Section 2. Support Technologies; Section 3. Integrated Circuit fabrication; Section 4. Test and Assembly; Section 5. Summary; Chapter 2. Support Technologies; Section 1. Introduction; Section 2. Contamination Control; Section 3. Crystal Growth and Wafer Preparation; Section 4. Circuit Design; Section 5. Photomask and Reticle Preparation; Chapter 3. Forming Wells; Section 1. Introduction.
- Section 2. Initial OxidationSection 3. Photolithography; Section 4. Ion Implantation; Chapter 4. Isolate Active Areas (Shallow Trench Isolation); Section 1. Introduction to Shallow Trench Isolation; Section 2. Pad Oxide Growth; Section 3. Silicon Nitride Deposition; Section 4. Photolithography for Photo/Etch; Section 5. Hard Mask Formation Using Plasma Etch; Section 6. Form Trenches in Silicon with Plasma Etch; Section 7. Fill Trenches with Silicon Dioxide; Section 8. Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9. Wet Etch Removal of Silicon Nitride and Pad Oxide.
- Chapter 5. Building the TransistorsSection 1. Introduction; Section 2. Thin Film Formation; Section 3. Poly Gate Formation; Section 4. Source/Drain Formation; Section 5. Salicide Formation; Chapter 6. First Level Metallization; Section 1. Introduction; Section 2. Nitride and Oxide Depositions ; Section 3. CMP Planarization; Section 4. Photo/Etch for Contact Holes; Section 5. Tungsten Plug Process; Section 6. Low-k Dielectric Process; Section 7. Copper First Level Interconnection Process; Chapter 7. Multilevel Metal Interconnects and Dual Damascene; Section 1. Introduction.
- Section 2. Deposit Barrier Layer and lntermetal DielectricSection 3. Dual Damascene Process; Section 4. Form Bonding Pads; Section 5. Final Passivation Process; Chapter 8. Test and Assembly; Section 1. Introduction; Section 2. Wafer and Chip Testing; Section 3. Assembly and Packaging; Appendix A. Science Overview; Introduction; Section 1. Atoms and Molecules; Section 2. Gases; Section 3. Chemistry; Section 4. Solids; Section 5. Electricity, Electric and Magnetic Fields; Appendix B. Plasma Etch Supplement to Chapter 4; Section 1. Plasma Etcher Theory.
- Section 2. Plasma Etch Process RequirementsBibliography; Index; ELSEVIER SCIENCE CD-ROM LICENSE AGREEMENT.