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ESD : Circuits and Devices.
ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Hoboken :
Wiley,
2015.
|
| Edición: | 2nd ed. |
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Title Page; Copyright Page; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Electrostatic Discharge ; 1.1 Electricity and Electrostatic Discharge; 1.1.1 Electricity and Electrostatics; 1.1.2 Electrostatic Discharge; 1.1.3 Key ESD Patents, Inventions, and Innovations; 1.1.4 Table of ESD Defect Mechanisms; 1.2 Fundamental Concepts of ESD Design; 1.2.1 Concepts of ESD Design; 1.2.2 Device Response to External Events; 1.2.3 Alternate Current Loops; 1.2.4 Switches; 1.2.5 Decoupling of Current Paths; 1.2.6 Decoupling of Feedback Loops; 1.2.7 Decoupling of Power Rails.
- 1.2.8 Local and Global Distribution1.2.9 Usage of Parasitic Elements; 1.2.10 Buffering; 1.2.11 Ballasting; 1.2.12 Unused Section of a Semiconductor Device, Circuit, or Chip Function; 1.2.13 Impedance Matching between Floating and Nonfloating Networks; 1.2.14 Unconnected Structures; 1.2.15 Utilization of Dummy Structures and Dummy Circuits; 1.2.16 Nonscalable Source Events; 1.2.17 Area Efficiency; 1.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup; 1.3.1 ESD; 1.3.2 Electrical Overstress; 1.3.3 Electromagnetic Interference; 1.3.4 Electromagnetic Compatibility; 1.3.5 Latchup.
- 1.4 ESD Models1.4.1 Human Body Model; 1.4.2 Machine Model; 1.4.3 Cassette Model (Small Charge Model); 1.4.4 Charged Device Model; 1.4.5 Transmission Line Pulse; 1.4.6 Very Fast Transmission Line Pulse; 1.5 ESD and System-Level Test Models; 1.5.1 IEC 61000-4-2; 1.5.2 Human Metal Model; 1.5.3 IEC 61000-4-5; 1.5.4 Charged Board Model; 1.5.5 Cable Discharge Event; 1.5.5.1 CDE and Scaling; 1.5.5.2 CDE-Cable Measurement Equipment; 1.5.5.3 Cable Configuration-Test Configuration; 1.5.5.4 Cable Configuration-Floating Cable; 1.5.5.5 Cable Configuration-Held Cable.
- 1.5.5.6 CDE-Peak Current versus Charged Voltage1.5.5.7 CDE-Plateau Current versus Charged Voltage; 1.6 Time Constants; 1.6.1 Characteristic Times; 1.6.2 Electrostatic and Magnetostatic Time Constants; 1.6.2.1 Charge Relaxation Time; 1.6.2.2 Magnetic Diffusion Time; 1.6.2.3 Electromagnetic Wave Transit Time; 1.6.3 Thermal Time Constants; 1.6.3.1 Heat Capacity; 1.6.3.2 Thermal Diffusion; 1.6.3.3 Heat Transport Equation; 1.6.4 Thermal Physics Time Constants; 1.6.4.1 Adiabatic, Thermal Diffusion Timescale, and Steady State; 1.6.5 Semiconductor Device Time Constants.
- 1.6.5.1 Depletion Region Transit Time1.6.5.2 Silicon Diode Storage Delay Time; 1.6.5.3 Bipolar Base Transit Time; 1.6.5.4 Bipolar Turn-on Transient Time; 1.6.5.5 Bipolar Turn-off Transient Time; 1.6.5.6 Bipolar Emitter Transition Capacitance Charging Time; 1.6.5.7 Bipolar Collector Capacitance Charging Time; 1.6.5.8 SCR Time Response; 1.6.5.9 MOSFET Transit Time; 1.6.5.10 MOSFET Drain Charging Time; 1.6.5.11 MOSFET Gate Charging Time; 1.6.5.12 MOSFET Parasitic Bipolar Response Time; 1.6.6 Circuit Time Constants; 1.6.6.1 Pad Capacitance; 1.6.6.2 Half-Pass TGs.