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A one-semester course in modeling of VLSI interconnections /

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-o...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Goel, Ashok K., 1953- (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Momentum Press, [2015]
Colección:Electronic circuits and semiconductor devices collection.
Temas:
Acceso en línea:Texto completo

MARC

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100 1 |a Goel, Ashok K.,  |d 1953-  |e author.  |1 https://id.oclc.org/worldcat/entity/E39PCjBHDkKkbtQmtv67qVfT9C 
245 1 2 |a A one-semester course in modeling of VLSI interconnections /  |c Ashok K. Goel. 
246 3 |a A one-semester course in modeling of very large-scale integration interconnections 
264 1 |a New York, NY :  |b Momentum Press,  |c [2015] 
264 4 |c ©2015 
300 |a 1 online resource (1 volume) :  |b illustrations 
336 |a text  |b txt  |2 rdacontent 
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490 1 |a Momentum Press electronic circuits and semiconductor devices collection 
588 0 |a Online resource; title from title page (Safari, viewed January 27, 2015). 
504 |a Includes bibliographical references and index. 
505 0 |a A One-Semester Course in Modeling of VLSI Interconnections; Dedication; Table of Contents; Preface; Acknowledgments; CHAPTER 1: Introductory Concepts; CHAPTER 2: Modeling of Interconnection Resistances, Capacitances, and Inductances; CHAPTER 3: Modeling of Interconnection Delays; CHAPTER 4: Modeling of InterconnectionCrosstalk; CHAPTER 5: Modeling of Electromigration-Induced Interconnection Failure; CHAPTER 6: Other Interconnection Technologies; APPENDIX A: Tables of Constants; APPENDIX B: Method of Images; APPENDIX C: Method of Moments; APPENDIX D: Transmission Line Equations. 
505 8 |a APPENDIX E: Miller's TheoremAPPENDIX F: Inverse Laplace Transformation Technique; Index; Ad page. 
520 |a Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-i. 
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650 0 |a Microelectronics  |x Mathematical models. 
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