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Networks-on-chip : from implementations to programming paradigms /
Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC a...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , , |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam :
Morgan Kaufmann,
2014.
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| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Front Cover; Networks-on-Chip: From Implementations to Programming Paradigms; Copyright; Contents in Brief; Contents; Preface; About the Editor-in-Chief and Authors; Editor-in-Chief; Authors; Part I: Prologue; Chapter 1: Introduction; 1.1 The dawn of the many-core era; 1.2 Communication-centric cross-layer optimizations; 1.3 A baseline design space exploration of NoCs; 1.3.1 Topology; 1.3.2 Routing algorithm; 1.3.3 Flow control; 1.3.4 Router microarchitecture; 1.3.5 Performance metric; 1.4 Review of NoC research; 1.4.1 Research on topologies; 1.4.2 Research on unicast routing.
- 1.4.3 Research on supporting collective communications1.4.4 Research on flow control; 1.4.5 Research on router microarchitecture; 1.5 Trends of real processors; 1.5.1 The MIT Raw processor; 1.5.2 The Tilera TILE64 processor; 1.5.3 The Sony/Toshiba/IBM Cell processor; 1.5.4 The U.T. Austin TRIPS processor; 1.5.5 The Intel Teraflops processor; 1.5.6 The Intel SCC processor; 1.5.7 The Intel Larrabee processor; 1.5.8 The Intel Knights Corner processor; 1.5.9 Summary of real processors; 1.6 Overview of the book; References; Part II: Logic implementations.
- Chapter 2: A single-cycle router with wing channels2.1 Introduction; 2.2 The router architecture; 2.2.1 The overall architecture; 2.2.2 Wing channels; 2.3 Microarchitecture designs; 2.3.1 Channel dispensers; 2.3.2 Fast arbiter components; 2.3.3 SIG managers and SIG controllers; 2.4 Experimental results; 2.4.1 Simulation infrastructures; 2.4.2 Pipeline delay analysis; 2.4.3 Latency and throughput; 2.4.4 Area and power consumption; 2.5 Chapter summary; References; Chapter 3: Dynamic virtual channel routers with congestion awareness; 3.1 Introduction; 3.2 DVC with congestion awareness.
- 3.2.1 DVC scheme3.2.2 Congestion avoidance scheme; 3.3 Multiple-port shared buffer with congestion awareness; 3.3.1 DVC scheme among multiple ports; 3.3.2 Congestion avoidance scheme; 3.4 DVC router microarchitecture; 3.4.1 VC control module; 3.4.2 Metric aggregation and congestion avoidance; 3.4.3 VC allocation module; 3.5 HiBB router microarchitecture; 3.5.1 VC control module; 3.5.2 VC allocation and output port allocation; 3.5.3 VC regulation; 3.6 Evaluation; 3.6.1 DVC router evaluation; 3.6.2 HiBB router evaluation; 3.7 Chapter summary; References.
- Chapter 4: Virtual bus structure-based network-on-chip topologies4.1 Introduction; 4.2 Background; 4.3 Motivation; 4.3.1 Baseline on-chip communication networks; 4.3.1.1 Transaction-based bus; 4.3.1.2 Packet-based NoC; 4.3.2 Analysis of NoC problems; 4.3.2.1 Multihop problem; 4.3.2.2 Multicast problem; 4.3.3 Advantages of a transaction-based bus; 4.4 The VBON; 4.4.1 Interconnect structures; 4.4.1.1 Wire delay consideration; 4.4.2 The VB mechanism; 4.4.2.1 The VB construction; 4.4.2.2 VB arbitration; 4.4.2.3 Packet format; 4.4.2.4 VB operation; 4.4.2.5 A simple example for VB communication.