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ESD : Analog Circuits and Design.
A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an intr...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Hoboken :
Wiley,
2014.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 035 | |a (OCoLC)886111716 | ||
| 050 | 4 | |a TK7867 .V43 2014 | |
| 082 | 0 | 4 | |a 621.3815 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Voldman, Steven H. | |
| 245 | 1 | 0 | |a ESD : |b Analog Circuits and Design. |
| 260 | |a Hoboken : |b Wiley, |c 2014. | ||
| 300 | |a 1 online resource (292 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress. | |
| 505 | 8 | |a 1.7.1 Electrical Overcurrent1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout. | |
| 505 | 8 | |a 2.1 Analog Design Layout Revisited2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout. | |
| 505 | 8 | |a 2.6.4 Thermoelectric Cancellation Layout2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror. | |
| 505 | 8 | |a 3.7 Voltage Regulators3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode. | |
| 500 | |a 4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET. | ||
| 520 | |a A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second. | ||
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Semiconductors |x Protection. | |
| 650 | 0 | |a Analog integrated circuits |x Protection. | |
| 650 | 0 | |a Analog integrated circuits |x Design and construction. | |
| 650 | 0 | |a Electrostatics. | |
| 650 | 0 | |a Static eliminators. | |
| 650 | 4 | |a Analog electronic systems |x Design and construction. | |
| 650 | 4 | |a Electric discharges. | |
| 650 | 4 | |a Electronic circuit design. | |
| 650 | 6 | |a Semi-conducteurs |x Protection. | |
| 650 | 6 | |a Circuits intégrés analogiques |x Protection. | |
| 650 | 6 | |a Antistatiques. | |
| 650 | 7 | |a antistatic agent. |2 aat | |
| 650 | 7 | |a Electrostatics |2 fast | |
| 650 | 7 | |a Semiconductors |x Protection |2 fast | |
| 650 | 7 | |a Static eliminators |2 fast | |
| 758 | |i has work: |a ESD Analog circuits and design (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGGT8cc6bGh8hHDycccXVC |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Voldman, Steven H. |t ESD : Analog Circuits and Design. |d Hoboken : Wiley, ©2014 |z 9781119965183 |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=1758401 |z Texto completo |
| 938 | |a EBL - Ebook Library |b EBLB |n EBL1758401 | ||
| 994 | |a 92 |b IZTAP | ||