Architectures for computer vision : from algorithm to chip with Verilog /

This book provides comprehensive coverage of 3D vision systems, from vision models and state-of-the-art algorithms to their hardware architectures for implementation on DSPs, FPGA and ASIC chips, and GPUs. It aims to fill the gaps between computer vision algorithms and real-time digital circuit impl...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Jeong, Hong
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Singapore : John Wiley & Sons Singapore Pte. Ltd., [2014]
Temas:
Verilog (Computer hardware description language)
Computer vision.
Verilog (Langage de description de matériel informatique)
Vision par ordinateur.
TECHNOLOGY & ENGINEERING > Mechanical.
Computer vision
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Architectures for Computer Vision
  • Contents
  • About the Author
  • Preface
  • Part One Verilog HDL
  • 1 Introduction
  • 1.1 Computer Architectures for Vision
  • 1.2 Algorithms for Computer Vision
  • 1.3 Computing Devices for Vision
  • 1.4 Design Flow for Vision Architectures
  • Problems
  • References
  • 2 Verilog HDL, Communication, and Control
  • 2.1 The Verilog System
  • 2.2 Hello, World!
  • 2.3 Modules and Ports
  • 2.4 UUT and TB
  • 2.5 Data Types and Operations
  • 2.6 Assignments
  • 2.7 Structural-Behavioral Design Elements
  • 2.8 Tasks and Functions
  • 2.9 Syntax Summary
  • 2.10 Simulation-Synthesis
  • 2.11 Verilog System Tasks and Functions
  • 2.12 Converting Vision Algorithms into Verilog HDL Codes
  • 2.13 Design Method for Vision Architecture
  • 2.14 Communication by Name Reference
  • 2.15 Synchronous Port Communication
  • 2.16 Asynchronous Port Communication
  • 2.17 Packing and Unpacking
  • 2.18 Module Control
  • 2.19 Procedural Block Control
  • Problems
  • References
  • 3 Processor, Memory, and Array
  • 3.1 Image Processing System
  • 3.2 Taxonomy of Algorithms and Architectures
  • 3.3 Neighborhood Processor
  • 3.4 BPBP Processor
  • 3.5 DP Processor
  • 3.6 Forward and Backward Processors
  • 3.7 Frame Buffer and Image Memory
  • 3.8 Multidimensional Array
  • 3.9 Queue
  • 3.10 Stack
  • 3.11 Linear Systolic Array
  • Problems
  • References
  • 4 Verilog Vision Simulator
  • 4.1 Vision Simulator
  • 4.2 Image Format Conversion
  • 4.3 Line-based Vision Simulator Principle
  • 4.4 LVSIM Top Module
  • 4.5 LVSIM IO System
  • 4.6 LVSIM RAM and Processor
  • 4.7 Frame-based Vision Simulator Principle
  • 4.8 FVSIM Top Module
  • 4.9 FVSIM IO System
  • 4.10 FVSIM RAM and Processor
  • 4.11 OpenCV Interface
  • Problems
  • References
  • Part Two Vision Principles
  • 5 Energy Function
  • 5.1 Discrete Labeling Problem
  • 5.2 MRF Model
  • 5.3 Energy Function.
  • 5.4 Energy Function Models
  • 5.5 Free Energy
  • 5.6 Inference Schemes
  • 5.7 Learning Methods
  • 5.8 Structure of the Energy Function
  • 5.9 Basic Energy Functions
  • Problems
  • References
  • 6 Stereo Vision
  • 6.1 Camera Systems
  • 6.2 Camera Matrices
  • 6.3 Camera Calibration
  • 6.4 Correspondence Geometry
  • 6.5 Camera Geometry
  • 6.6 Scene Geometry
  • 6.7 Rectification
  • 6.8 Appearance Models
  • 6.9 Fundamental Constraints
  • 6.10 Segment Constraints
  • 6.11 Constraints in Discrete Space
  • 6.12 Constraints in Frequency Space
  • 6.13 Basic Energy Functions
  • Problems
  • References
  • 7 Motion and Vision Modules
  • 7.1 3D Motion
  • 7.2 Direct Motion Estimation
  • 7.3 Structure from Optical Flow
  • 7.4 Factorization Method
  • 7.5 Constraints on the Data Term
  • 7.6 Continuity Equation
  • 7.7 The Prior Term
  • 7.8 Energy Minimization
  • 7.9 Binocular Motion
  • 7.10 Segmentation Prior
  • 7.11 Blur Diameter
  • 7.12 Blur Diameter and Disparity
  • 7.13 Surface Normal and Disparity
  • 7.14 Surface Normal and Blur Diameter
  • 7.15 Links between Vision Modules
  • Problems
  • References
  • Part Three Vision Architectures
  • 8 Relaxation for Energy Minimization
  • 8.1 Euler-Lagrange Equation of the Energy Function
  • 8.2 Discrete Diffusion and Biharminic Operators
  • 8.3 SOR Equation
  • 8.4 Relaxation Equation
  • 8.5 Relaxation Graph
  • 8.6 Relaxation Machine
  • 8.7 Affine Graph
  • 8.8 Fast Relaxation Machine
  • 8.9 State Memory of Fast Relaxation Machine
  • 8.10 Comparison of Relaxation Machines
  • Problems
  • References
  • 9 Dynamic Programming for Energy Minimization
  • 9.1 DP for Energy Minimization
  • 9.2 N-best Parallel DP
  • 9.3 N-best Serial DP
  • 9.4 Extended DP
  • 9.5 Hidden Markov Model
  • 9.6 Inside-Outside Algorithm
  • Problems
  • References
  • 10 Belief Propagation and Graph Cuts for Energy Minimization
  • 10.1 Belief in MRF Factor System.
  • 10.2 Belief in Pairwise MRF System
  • 10.3 BP in Discrete Space
  • 10.4 BP in Vector Space
  • 10.5 Flow Network for Energy Function
  • 10.6 Swap Move Algorithm
  • 10.7 Expansion Move Algorithm
  • Problems
  • References
  • Part Four Verilog Design
  • 11 Relaxation for Stereo Matching
  • 11.1 Euler-Lagrange Equation
  • 11.2 Discretization and Iteration
  • 11.3 Relaxation Algorithm for Stereo Matching
  • 11.4 Relaxation Machine
  • 11.5 Overall System
  • 11.6 IO Circuit
  • 11.7 Updation Circuit
  • 11.8 Circuit for the Data Term
  • 11.9 Circuit for the Differential
  • 11.10 Circuit for the Neighborhood
  • 11.11 Functions for Saturation Arithmetic
  • 11.12 Functions for Minimum Argument
  • 11.13 Simulation
  • Problems
  • References
  • 12 Dynamic Programming for Stereo Matching
  • 12.1 Search Space
  • 12.2 Line Processing
  • 12.3 Computational Space
  • 12.4 Energy Equations
  • 12.5 DP Algorithm
  • 12.6 Architecture
  • 12.7 Overall Scheme
  • 12.8 FIFO Buffer
  • 12.9 Reading and Writing
  • 12.10 Initialization
  • 12.11 Forward Pass
  • 12.12 Backward Pass
  • 12.13 Combinational Circuits
  • 12.14 Simulation
  • Problems
  • References
  • 13 Systolic Array for Stereo Matching
  • 13.1 Search Space
  • 13.2 Systolic Transformation
  • 13.3 Fundamental Systolic Arrays
  • 13.4 Search Spaces of the Fundamental Systolic Arrays
  • 13.5 Systolic Algorithm
  • 13.6 Common Platform of the Circuits
  • 13.7 Forward Backward and Right Left Algorithm
  • 13.8 FBR and FBL Overall Scheme
  • 13.9 FBR and FBL FIFO Buffer
  • 13.10 FBR and FBL Reading and Writing
  • 13.11 FBR and FBL Preprocessing
  • 13.12 FBR and FBL Initialization
  • 13.13 FBR and FBL Forward Pass
  • 13.14 FBR and FBL Backward Pass
  • 13.15 FBR and FBL Simulation
  • 13.16 Backward Backward and Right Left Algorithm
  • 13.17 BBR and BBL Overall Scheme
  • 13.18 BBR and BBL Initialization
  • 13.19 BBR and BBL Forward Pass.
  • 13.20 BBR and BBL Backward Pass
  • 13.21 BBR and BBL Simulation
  • Problems
  • References
  • 14 Belief Propagation for Stereo Matching
  • 14.1 Message Representation
  • 14.2 Window Processing
  • 14.3 BP Machine
  • 14.4 Overall System
  • 14.5 IO Circuit
  • 14.6 Sampling Circuit
  • 14.7 Circuit for the Data Term
  • 14.8 Circuit for the Input Belief Message Matrix
  • 14.9 Circuit for the Output Belief Message Matrix
  • 14.10 Circuit for the Updation of Message Matrix
  • 14.11 Circuit for the Disparity
  • 14.12 Saturation Arithmetic
  • 14.13 Smoothness
  • 14.14 Minimum Argument
  • 14.15 Simulation
  • Problems
  • References
  • Index
  • EULA.

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