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Design and modeling for 3d ics and interposers.
3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the Silicon Via (TSV) and Glass Via (TGV) technology,...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
WSPC,
2013.
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| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Preface; Contents; Acknowledgement; Chapter 1: System Integration and Modeling Concepts; 1.1 Moore's Law; 1.2 IC Integration Vs System Integration
- What is the Difference?; 1.3 History of Integration
- An Overview; 1.3.1 3D Integration
- Is it the Next Semiconductor Revolution?; 1.3.2 What Comes Next?; 1.4 Primary Drivers for 3D Integration; 1.4.1 Thirst for More Bandwidth at Low Power; 1.4.2 Large Chips Sink Ships; 1.4.3 Heterogeneous Integration to Continue More Than Moore Scaling; 1.5 Role of the Interposer in 3D Integration; 1.5.1 Three Embodiments of the Interposer
- 1.5.2 Silicon or Glass or X for Interposer 1.6 Modeling and Simulation; 1.6.1 Electrical Modeling and 3D Path Finder; 1.6.1.1 Full Wave Electromagnetic Analysis; 1.6.1.2 Physics Based Analytical Models; 1.6.1.3 3D Path Finder; 1.6.2 Design Exchange Format; 1.6.2.1 Example of a Two Die Stack; 1.6.2.2 IR Drop; 1.6.2.3 Thermal Management; 1.6.2.4 Move Towards a DEF by the Engineering Community; 1.7 Summary; References; Chapter 2: Modeling of Cylindrical Interconnections; 2.1 Introduction; 2.2 Specialized Basis Functions
- 2.3 Electric Field Integral Equation (EFIE) with Cylindrical CMBF for Resistance and Inductance Extraction 2.3.1 Cylindrical Conduction Mode Basis Functions (CMBF); 2.3.2 EFIE Formulation; 2.3.2.1 Voltage Equation; 2.3.2.2 Partial Impedances; 2.3.2.3 Equivalent Circuit; 2.3.3 Efficiency Enhancements and Implementation; 2.3.3.1 Controlling the Number of PE-Mode Basis Functions; 2.3.3.2 Multi-Function Method (MFM); 2.3.4 R-L Extraction Example: Comparison with PEEC Method; 2.4 Scalar Potential Integral Equation (SPIE) with Cylindrical AMBF for Conductance and Capacitance Extraction
- 2.4.1 Cylindrical Accumulation Mode Basis Functions (AMBF)2.4.2 SPIE Formulation in Free Space; 2.4.3 SPIE Formulation Considering Homogeneous Media; 2.4.3.1 Vector and Scalar Potentials; 2.4.3.2 Equivalent Circuit Model of Conductor; 2.5 Broadband Equivalent RLC Network; 2.6 Inclusion of Planar Structures; 2.6.1 Combining Cylindrical and Planar Structures; 2.6.1.1 Conventional PEEC Method; 2.6.2 Infinite Ground Plane: Image Method for Modeling Infinite Ground; 2.7 Examples with Bonding Wires; 2.7.1 Three JEDEC4 Type Bonding Wires
- 2.7.2 Bonding Wires in a Plastic Ball Grid Array (PBGA) Package 2.7.3 Bonding Wires in Three Stacked ICs: The Effect of Vertical Coupling; 2.8 Examples with Vias; 2.8.1 Glass Interposer Vias; 2.8.2 Via Chains; 2.9 Example of Package on Package; 2.10 Summary; References; Chapter 3: Electrical Modeling of Through Silicon Vias; 3.1 Benefits of Through Silicon Vias; 3.2 Challenges in Modeling Through Silicon Vias; 3.3 Propagating Modes in Through Silicon Vias
- An Electromagnetic Perspective; 3.4 Physics Based Modeling of Through Silicon Vias; 3.4.1 Creating an Equivalent Circuit