Cargando…
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design.
This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The books covers the essential issues associated with fast and effective integration of reusable design...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Norwood :
Artech House,
2009.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000Mu 4500 | ||
|---|---|---|---|
| 001 | EBOOKCENTRAL_ocn796382975 | ||
| 003 | OCoLC | ||
| 005 | 20240329122006.0 | ||
| 006 | m o d | ||
| 007 | cr unu|||||||| | ||
| 008 | 121121s2009 xx o 000 0 eng d | ||
| 040 | |a EBLCP |b eng |e pn |c EBLCP |d OCLCQ |d DEBSZ |d OCLCQ |d ZCU |d MERUC |d U3W |d OCLCF |d OCLCO |d OCLCQ |d OCLCO |d ICG |d INT |d OCLCQ |d DKC |d AU@ |d OCLCQ |d OCLCO |d OCLCQ |d STF |d OCLCO |d OCLCL | ||
| 019 | |a 1388674982 | ||
| 020 | |a 9781596934252 | ||
| 020 | |a 1596934255 | ||
| 020 | |a 9781596934245 |q (print) | ||
| 020 | |a 1596934247 | ||
| 029 | 1 | |a DEBBG |b BV044166452 | |
| 029 | 1 | |a DEBSZ |b 431153779 | |
| 029 | 1 | |a DEBSZ |b 45649619X | |
| 035 | |a (OCoLC)796382975 |z (OCoLC)1388674982 | ||
| 050 | 4 | |a QA76.76 .R47 M328 2009 | |
| 072 | 0 | |a TEC008070 | |
| 072 | 0 | |a TEC007000 | |
| 082 | 0 | 4 | |a 621.39 |a 621.3916 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Mathaikutty, Deepak A. | |
| 245 | 1 | 0 | |a Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design. |
| 260 | |a Norwood : |b Artech House, |c 2009. | ||
| 300 | |a 1 online resource (310 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 505 | 0 | |a Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider. | |
| 505 | 8 | |a Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation. | |
| 505 | 8 | |a 2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION. | |
| 505 | 8 | |a 3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection. | |
| 505 | 8 | |a 5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY. | |
| 520 | |a This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The books covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a?write once, use many times? verification strategy? another effective approach that can attain a faster product design cycle. | ||
| 588 | 0 | |a Print version record. | |
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Computer software |x Reusability. | |
| 650 | 0 | |a Computer software |x Verification. | |
| 650 | 0 | |a Intellectual property. | |
| 650 | 0 | |a Microprocessors |x Design and construction. | |
| 650 | 0 | |a System design. | |
| 650 | 0 | |a Systems on a chip |x Design and construction. | |
| 650 | 2 | |a Intellectual Property | |
| 650 | 6 | |a Logiciels |x Réutilisation. | |
| 650 | 6 | |a Logiciels |x Vérification. | |
| 650 | 6 | |a Propriété intellectuelle. | |
| 650 | 6 | |a Conception de systèmes. | |
| 650 | 7 | |a intellectual property. |2 aat | |
| 650 | 7 | |a Computer software |x Reusability |2 fast | |
| 650 | 7 | |a Computer software |x Verification |2 fast | |
| 650 | 7 | |a Intellectual property |2 fast | |
| 650 | 7 | |a Microprocessors |x Design and construction |2 fast | |
| 650 | 7 | |a System design |2 fast | |
| 650 | 7 | |a Systems on a chip |x Design and construction |2 fast | |
| 700 | 1 | |a Shukla, Sandeep. | |
| 758 | |i has work: |a Metamodeling-driven IP reuse for SoC integration and microprocessor design (Text) |1 https://id.oclc.org/worldcat/entity/E39PCFPtcHTrvrTpQHtvj8ybFq |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Mathaikutty, Deepak A. |t Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design. |d Norwood : Artech House, ©2009 |z 9781596934245 |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=946534 |z Texto completo |
| 938 | |a ProQuest Ebook Central |b EBLB |n EBL946534 | ||
| 994 | |a 92 |b IZTAP | ||