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Engineering the CMOS library : enhancing digital design kits for competitive silicon /
"This book is about gaining a competitive edge in the Integrated Circuit IC marketplace. It suggests that there is an unrecognized value hidden in the safety margins of descriptive views in any piece of intellectual property (IP). This hidden value is normally left on the table. However, it can...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Hoboken, N.J. :
John Wiley & Sons,
©2012.
|
| Temas: | |
| Acceso en línea: | Texto completo Texto completo |
MARC
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| 100 | 1 | |a Doman, David. | |
| 245 | 1 | 0 | |a Engineering the CMOS library : |b enhancing digital design kits for competitive silicon / |c David Doman. |
| 260 | |a Hoboken, N.J. : |b John Wiley & Sons, |c ©2012. | ||
| 300 | |a 1 online resource (iv, 327 pages) : |b illustrations | ||
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| 520 | |a "This book is about gaining a competitive edge in the Integrated Circuit IC marketplace. It suggests that there is an unrecognized value hidden in the safety margins of descriptive views in any piece of intellectual property (IP). This hidden value is normally left on the table. However, it can be used by the aggressive design engineer (or manager) to surpass the competition in the marketplace. This text reveals how the typical design house can enhance performance, reduce power, and improve the density of standard-cell logic. It will show how to add value to the generic, foundry-provided standard-cell library that most companies use without modification. Lastly, it identifies the low-risk opportunities aggressive designers and managers can employ to improve margin from overdesigned standard cells."-- |c Provided by publisher. | ||
| 520 | |a "This book is about gaining a competitive edge in the Integrated Circuit IC marketplace"-- |c Provided by publisher. | ||
| 505 | 0 | |a Frontmatter -- Introduction -- Stdcell Libraries -- IO Libraries -- Memory Compilers -- Other Functions -- Physical Views -- Spice -- Timing Views -- Power Views -- Noise Views -- Logical Views -- Test Views -- Consistency -- Design for Manufacturability -- Validation -- Playing with the Physical Design Kit: Usually ₃At Your Own Risk₄ -- Tagging and Revisioning -- Releasing and Supporting -- Other Topics -- Communications -- Appendix I: Minimum Library Synthesis Versus Full-Library Synthesis of A Four-Bit Flash Adder -- Appendix II: Pertinent CMOS Bsim Spice Parameters with Units and Default Levels -- Appendix III: Definition of Terms -- Appendix IV: One Possible Means of Formalized Monthly Reporting -- Index. | |
| 588 | 0 | |a Print version record. | |
| 546 | |a English. | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Digital integrated circuits |x Design and construction. | |
| 650 | 0 | |a Metal oxide semiconductors, Complementary. | |
| 650 | 0 | |a Industrial efficiency. | |
| 650 | 6 | |a Circuits intégrés numériques |x Conception et construction. | |
| 650 | 6 | |a MOS complémentaires. | |
| 650 | 6 | |a Efficience dans l'industrie. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x General. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Integrated. |2 bisacsh | |
| 650 | 7 | |a Digital integrated circuits |x Design and construction |2 fast | |
| 650 | 7 | |a Industrial efficiency |2 fast | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary |2 fast | |
| 758 | |i has work: |a Engineering the CMOS library (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGKryYV9JGrtKx9G46RGwP |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Doman, David. |t Engineering the CMOS library. |d Hoboken, N.J. : John Wiley & Sons, ©2012 |z 9781118243046 |w (DLC) 2011043303 |w (OCoLC)755700209 |
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