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Design for embedded image processing on FPGAs /
"Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardwa...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Singapore :
IEEE : John Wiley & Sons (Asia),
2011.
|
| Temas: | |
| Acceso en línea: | Texto completo Texto completo |
MARC
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| 100 | 1 | |a Bailey, Donald G. |q (Donald Graeme), |d 1962- |e author. |4 aut | |
| 245 | 1 | 0 | |a Design for embedded image processing on FPGAs / |c Donald G. Bailey. |
| 264 | 1 | |a Singapore : |b IEEE : |b John Wiley & Sons (Asia), |c 2011. | |
| 264 | 4 | |c ©2011 | |
| 300 | |a 1 online resource (xvi, 482 pages, 6 unnumbered pages of plates) : |b illustrations (some color) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a data file | ||
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | 0 | |g 1. |t Image Processing -- |g 1.1. |t Basic Definitions -- |g 1.2. |t Image Formation -- |g 1.3. |t Image Processing Operations -- |g 1.4. |t Example Application -- |g 1.5. |t Real-Time Image Processing -- |g 1.6. |t Embedded Image Processing -- |g 1.7. |t Serial Processing -- |g 1.8. |t Parallelism -- |g 1.9. |t Hardware Image Processing Systems -- |g 2. |t Field Programmable Gate Arrays -- |g 2.1. |t Programmable Logic -- |g 2.2. |t FPGAs and Image Processing -- |g 2.3. |t Inside an FPGA -- |g 2.4. |t FPGA Families and Features -- |g 2.5. |t Choosing an FPGA or Development Board -- |g 3. |t Languages -- |g 3.1. |t Hardware Description Languages -- |g 3.2. |t Software-Based Languages -- |g 3.3. |t Visual Languages -- |g 3.4. |t Summary -- |g 4. |t Design Process -- |g 4.1. |t Problem Specification -- |g 4.2. |t Algorithm Development -- |g 4.3. |t Architecture Selection -- |g 4.4. |t System Implementation -- |g 4.5. |t Designing for Tuning and Debugging -- |g 5. |t Mapping Techniques -- |g 5.1. |t Timing Constraints -- |g 5.2. |t Memory Bandwidth Constraints -- |g 5.3. |t Resource Constraints -- |g 5.4. |t Computational Techniques -- |g 5.5. |t Summary -- |g 6. |t Point Operations -- |g 6.1. |t Point Operations on a Single Image -- |g 6.2. |t Point Operations on Multiple Images -- |g 6.3. |t Colour Image Processing -- |g 6.4. |t Summary -- |g 7. |t Histogram Operations -- |g 7.1. |t Greyscale Histogram -- |g 7.2. |t Multidimensional Histograms -- |g 8. |t Local Filters -- |g 8.1. |t Caching -- |g 8.2. |t Linear Filters -- |g 8.3. |t Nonlinear Filters -- |g 8.4. |t Rank Filters -- |g 8.5. |t Colour Filters -- |g 8.6. |t Morphological Filters -- |g 8.7. |t Adaptive Thresholding -- |g 8.8. |t Summary -- |g 9. |t Geometric Transformations -- |g 9.1. |t Forward Mapping -- |g 9.2. |t Reverse Mapping -- |g 9.3. |t Interpolation -- |g 9.4. |t Mapping Optimisations -- |g 9.5. |t Image Registration -- |g 10. |t Linear Transforms -- |g 10.1. |t Fourier Transform -- |g 10.2. |t Discrete Cosine Transform -- |g 10.3. |t Wavelet Transform -- |g 10.4. |t Image and Video Coding -- |g 11. |t Blob Detection and Labelling -- |g 11.1. |t Bounding Box -- |g 11.2. |t Run-Length Coding -- |g 11.3. |t Chain Coding -- |g 11.4. |t Connected Component Labelling -- |g 11.5. |t Distance Transform -- |g 11.6. |t Watershed Transform -- |g 11.7. |t Hough Transform -- |g 11.8. |t Summary -- |g 12. |t Interfacing -- |g 12.1. |t Camera Input -- |g 12.2. |t Display Output -- |g 12.3. |t Serial Communication -- |g 12.4. |t Memory -- |g 12.5. |t Summary -- |g 13. |t Testing, Tuning and Debugging -- |g 13.1. |t Design -- |g 13.2. |t Implementation -- |g 13.3. |t Tuning -- |g 13.4. |t Timing Closure -- |g 14. |t Example Applications -- |g 14.1. |t Coloured Region Tracking -- |g 14.2. |t Lens Distortion Correction -- |g 14.3. |t Foveal Sensor -- |g 14.4. |t Range Imaging -- |g 14.5. |t Real-Time Produce Grading -- |g 14.6. |t Summary. |
| 520 | |a "Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned. Provides a bridge between algorithms and hardware. Demonstrates how to avoid many of the potential pitfalls. Offers practical recommendations and solutions. Illustrates several real-world applications and case studies. Allows those with software backgrounds to understand efficient hardware implementation."--Publisher's description | ||
| 520 | |a "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- |c Provided by publisher | ||
| 588 | 0 | |a Print version record and online resource; title from PDF title page (IEEE Xplore, viewed March 14, 2014). | |
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Embedded computer systems. | |
| 650 | 0 | |a Field programmable gate arrays. | |
| 650 | 6 | |a Systèmes enfouis (Informatique) | |
| 650 | 6 | |a Réseaux logiques programmables par l'utilisateur. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Microelectronics. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Computer Engineering. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Hardware |x General. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Machine Theory. |2 bisacsh | |
| 650 | 7 | |a Embedded computer systems |2 fast | |
| 650 | 7 | |a Field programmable gate arrays |2 fast | |
| 758 | |i has work: |a Design for embedded image processing on FPGAs (Text) |1 https://id.oclc.org/worldcat/entity/E39PCH7xjbDKcG9TyjMT8PPD4m |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
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