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VHDL for Logic Synthesis.
Making VHDL a simple and easy-to-use hardware description languageMany engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Hoboken :
John Wiley & Sons,
2011.
|
| Edición: | 3rd ed. |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Rushton, Andrew. | |
| 245 | 1 | 0 | |a VHDL for Logic Synthesis. |
| 250 | |a 3rd ed. | ||
| 260 | |a Hoboken : |b John Wiley & Sons, |c 2011. | ||
| 300 | |a 1 online resource (1036 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 505 | 0 | |a Cover; Title Page; Copyright; Preface; List of Figures; List of Tables; Chapter 1: Introduction; Chapter 2: Register-Transfer Level Design; Chapter 3: Combinational Logic; Chapter 4: Basic Types; Chapter 5: Operators; Chapter 6: Synthesis Types; Chapter 7: Std_Logic_Arith; Chapter 8: Sequential VHDL; Chapter 9: Registers; Chapter 10: Hierarchy; Chapter 11: Subprograms; Chapter 12: Special Structures; Chapter 13: Test Benches; Chapter 14: Libraries; Chapter 15: Case Study; Appendix A: Package Listings; Appendix B: Syntax Reference; References; Index. | |
| 520 | |a Making VHDL a simple and easy-to-use hardware description languageMany engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range o. | ||
| 588 | 0 | |a Print version record. | |
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | |a Logic design |x Data processing. | |
| 650 | 0 | |a Computer-aided design. | |
| 650 | 6 | |a VHDL (Langage de description de matériel informatique) | |
| 650 | 6 | |a Structure logique |x Informatique. | |
| 650 | 6 | |a Conception assistée par ordinateur. | |
| 650 | 7 | |a computer-aided designs (visual works) |2 aat | |
| 650 | 7 | |a computer-aided design (process) |2 aat | |
| 650 | 7 | |a Computer-aided design |2 fast | |
| 650 | 7 | |a Logic design |x Data processing |2 fast | |
| 650 | 7 | |a VHDL (Computer hardware description language) |2 fast | |
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| 776 | 0 | 8 | |i Print version: |a Rushton, Andrew. |t VHDL for Logic Synthesis. |d Hoboken : John Wiley & Sons, Ltd., ©2011 |z 9780470688472 |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=675308 |z Texto completo |
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