Design Methodology for RF CMOS Phase Locked Loops.

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After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block.

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Bistue, Guillermo
Otros Autores: Adin, Inigo, Quemada, Carlos
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Norwood : Artech House, 2008.
Temas:
Metal oxide semiconductors, Complementary > Design and construction.
Phase-locked loops > Design and construction.
Metal oxide semiconductors, Complementary > Design and construction
Phase-locked loops > Design and construction
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Design Methodology for RF CMOS Phase Locked Loops; Contents; Preface; 1 Approach to CMOS PLL Design; 2 PLL Fundamentals; 3 LC-Tank Integrated Oscillators; 4 Frequency Divider; 5 Phase Frequency Detector/Phase Detector; 6 Determination of Building Blocks Specifications; 7 Design of a 3.2-GHz CMOS VCO; 8 Design of a Frequency Divider; 9 Design of a Phase Frequency Detector; 10 Design of the Complete PLL; 11 PLL Characterization and Results; About the Authors; Index.

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