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Design Methodology for RF CMOS Phase Locked Loops.
After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block.
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Norwood :
Artech House,
2008.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 003 | OCoLC | ||
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| 020 | |a 9781596933842 |q (electronic bk.) | ||
| 020 | |a 1596933844 |q (electronic bk.) | ||
| 020 | |a 9781596933835 |q (print) | ||
| 020 | |a 1596933836 | ||
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| 049 | |a UAMI | ||
| 100 | 1 | |a Bistue, Guillermo. | |
| 245 | 1 | 0 | |a Design Methodology for RF CMOS Phase Locked Loops. |
| 260 | |a Norwood : |b Artech House, |c 2008. | ||
| 300 | |a 1 online resource (242 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 505 | 0 | |a Design Methodology for RF CMOS Phase Locked Loops; Contents; Preface; 1 Approach to CMOS PLL Design; 2 PLL Fundamentals; 3 LC-Tank Integrated Oscillators; 4 Frequency Divider; 5 Phase Frequency Detector/Phase Detector; 6 Determination of Building Blocks Specifications; 7 Design of a 3.2-GHz CMOS VCO; 8 Design of a Frequency Divider; 9 Design of a Phase Frequency Detector; 10 Design of the Complete PLL; 11 PLL Characterization and Results; About the Authors; Index. | |
| 520 | |a After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. | ||
| 588 | 0 | |a Print version record. | |
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Metal oxide semiconductors, Complementary |x Design and construction. | |
| 650 | 0 | |a Phase-locked loops |x Design and construction. | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary |x Design and construction |2 fast | |
| 650 | 7 | |a Phase-locked loops |x Design and construction |2 fast | |
| 700 | 1 | |a Adin, Inigo. | |
| 700 | 1 | |a Quemada, Carlos. | |
| 758 | |i has work: |a Design methodology for RF CMOS phase locked loops (Text) |1 https://id.oclc.org/worldcat/entity/E39PCH6x9w67g6K7Y7cfvT8qHC |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 1 | |z 9781596933835 | |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=456885 |z Texto completo |
| 938 | |a EBL - Ebook Library |b EBLB |n EBL456885 | ||
| 994 | |a 92 |b IZTAP | ||