Verification Techniques for System-Level Design.

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A must-read in formal and semi-formal verification!

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Fujita, Masahiro
Otros Autores: Ghosh, Indradeep, Prasad, Mukul
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Burlington : Elsevier, 2007.
Colección:Morgan Kaufmann series in systems on silicon.
Temas:
Systems on a chip > Testing.
Integrated circuits > Verification.
Formal methods (Computer science)
Circuits intégrés > Vérification.
Méthodes formelles (Informatique)
Integrated circuits > Verification
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Front Cover; Verification Techniques For System-Level Design; Copyright Page; Contents; Acknowledgments; Chapter 1 Introduction; Chapter 2 Higher-Level Design Methodology and Associated Verification Problems; Chapter 3 Basic Technology for Formal Verification; Chapter 4 Verification Algorithms for FSM Models; Chapter 5 Static Checking of Higher-Level Design Descriptions; Chapter 6 Equivalence Checking on Higher-Level Design Descriptions; Chapter 7 Model Checking on Higher-Level Design Descriptions; Chapter 8 Simulation-Based Verification Techniques for System-Level Designs.
  • Chapter 9 ConclusionIndex.

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