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Verification Techniques for System-Level Design.
A must-read in formal and semi-formal verification!
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Burlington :
Elsevier,
2007.
|
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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|---|---|---|---|
| 001 | EBOOKCENTRAL_ocn437191662 | ||
| 003 | OCoLC | ||
| 005 | 20240329122006.0 | ||
| 006 | m o d | ||
| 007 | cr mn|---||||| | ||
| 008 | 090817s2007 vtu o 000 0 eng d | ||
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| 050 | 4 | |a TK7895.E42 | |
| 082 | 0 | 4 | |a 621.3815 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Fujita, Masahiro. | |
| 245 | 1 | 0 | |a Verification Techniques for System-Level Design. |
| 260 | |a Burlington : |b Elsevier, |c 2007. | ||
| 300 | |a 1 online resource (251 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a Systems on Silicon | |
| 505 | 0 | |a Front Cover; Verification Techniques For System-Level Design; Copyright Page; Contents; Acknowledgments; Chapter 1 Introduction; Chapter 2 Higher-Level Design Methodology and Associated Verification Problems; Chapter 3 Basic Technology for Formal Verification; Chapter 4 Verification Algorithms for FSM Models; Chapter 5 Static Checking of Higher-Level Design Descriptions; Chapter 6 Equivalence Checking on Higher-Level Design Descriptions; Chapter 7 Model Checking on Higher-Level Design Descriptions; Chapter 8 Simulation-Based Verification Techniques for System-Level Designs. | |
| 505 | 8 | |a Chapter 9 ConclusionIndex. | |
| 520 | |a A must-read in formal and semi-formal verification! | ||
| 588 | 0 | |a Print version record. | |
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Systems on a chip |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Verification. | |
| 650 | 0 | |a Formal methods (Computer science) | |
| 650 | 6 | |a Circuits intégrés |x Vérification. | |
| 650 | 6 | |a Méthodes formelles (Informatique) | |
| 650 | 7 | |a Formal methods (Computer science) |2 fast | |
| 650 | 7 | |a Integrated circuits |x Verification |2 fast | |
| 700 | 1 | |a Ghosh, Indradeep. | |
| 700 | 1 | |a Prasad, Mukul. | |
| 758 | |i has work: |a Verification techniques for system-level design (Text) |1 https://id.oclc.org/worldcat/entity/E39PCG7DGGQPHGyqGCXc443WWC |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 1 | |z 9780123706164 | |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=318151 |z Texto completo |
| 938 | |a EBL - Ebook Library |b EBLB |n EBL318151 | ||
| 938 | |a ProQuest MyiLibrary Digital eBook Collection |b IDEB |n 104964 | ||
| 994 | |a 92 |b IZTAP | ||