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Nano-CMOS circuit and physical design /
Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Hoboken, N.J. :
John Wiley,
©2005.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 245 | 0 | 0 | |a Nano-CMOS circuit and physical design / |c Ban P. Wong [and others]. |
| 260 | |a Hoboken, N.J. : |b John Wiley, |c ©2005. | ||
| 300 | |a 1 online resource (xviii, 393 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a data file | ||
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a COVER -- TABLE OF CONTENTS -- FOREWORD -- PREFACE -- CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS -- 1.1 Design Methodology in the Nano-CMOS Era -- 1.2 Innovations Needed to Continue Performance Scaling -- 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography -- 1.3.1 Back-End-of-Line Challenges (Metallization) -- 1.3.2 Front-End-of-Line Challenges (Transistors) -- 1.4 Process Control and Reliability -- 1.5 Lithographic Issues and Mask Data Explosion -- 1.6 New Breed of Circuit and Physical Design Engineers -- 1.7 Modeling Challenges -- 1.8 Need for Design Methodology Changes -- 1.9 Summary -- References -- PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS -- CHAPTER 2 CMOS DEVICE AND PROCESS TECHNOLOGY -- 2.1 Equipment Requirements for Front-End Processing -- 2.2 Front-End-Device Problems in CMOS Scaling -- 2.3 Back-End-of-Line Technology -- References -- CHAPTER 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY -- 3.1 Introduction and Simple Imaging Theory -- 3.2 Challenges for the 100-nm Node -- 3.3 Resolution Enhancement Techniques: Physics -- 3.4 Physical Design Style Impact on RET and OPC Complexity -- 3.5 The Road Ahead: Future Lithographic Technologies -- References -- PART II PROCESS SCALING IMPACT ON DESIGN -- CHAPTER 4 MIXED-SIGNAL CIRCUIT DESIGN -- 4.1 Introduction -- 4.2 Design Considerations -- 4.3 Device Modeling -- 4.4 Passive Components -- 4.5 Design Methodology -- 4.6 Low-Voltage Techniques -- 4.7 Design Procedures -- 4.8 Electrostatic Discharge Protection -- 4.9 Noise Isolation -- 4.10 Decoupling -- 4.11 Power Busing -- 4.12 Integration Problems -- 4.13 Summary -- References -- CHAPTER 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN -- 5.1 Introduction -- 5.2 ESD Standards and Models -- 5.3 ESD Protection Design -- 5.4 Low-C ESD Protection Design for High-Speed I/O -- 5.5 ESD Protection Design for Mixed-Voltage I/O -- 5.6 SCR Devices for ESD Protection -- 5.7 Summary -- References -- CHAPTER 6 INPUT/OUTPUT DESIGN -- 6.1 Introduction -- 6.2 I/O Standards -- 6.3 Signal Transfer -- 6.4 ESD Protection -- 6.5 I/O Switching Noise -- 6.6 Termination -- 6.7 Impedance Matching -- 6.8 Preemphasis -- 6.9 Equalization -- 6.10 Conclusion -- References -- CHAPTER 7 DRAM -- 7.1 Introduction -- 7.2 DRAM Basics -- 7.3 Scaling the Capacitor -- 7.4 Scaling the Array Transistor -- 7.5 Scaling the Sense Amplifier -- 7.6 Summary -- References -- CHAPTER 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS -- 8.1 Introduction -- 8.2 Interconnect Parasitics Extraction -- 8.3 Signal Integrity Analysis -- 8.4 Design Solutions for Signal Integrity -- 8.5 Summary -- References -- CHAPTER 9 ULTRALOW POWER CIRCUIT DESIGN -- 9.1 Introduction -- 9.2 Design-Time Low-Power Techniques -- 9.3 Run-Time Low-Power Techniques -- 9.4 Technology Innovations for Low-Power Design -- 9.5 Perspectives for Future Ultralow-Power Design -- References -- PART III IMPA. | |
| 520 | |a Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation. | ||
| 588 | 0 | |a Print version record. | |
| 506 | |3 Use copy |f Restrictions unspecified |2 star |5 MiAaHDL | ||
| 533 | |a Electronic reproduction. |b [Place of publication not identified] : |c HathiTrust Digital Library, |d 2010. |5 MiAaHDL | ||
| 538 | |a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. |u http://purl.oclc.org/DLF/benchrepro0212 |5 MiAaHDL | ||
| 583 | 1 | |a digitized |c 2010 |h HathiTrust Digital Library |l committed to preserve |2 pda |5 MiAaHDL | |
| 546 | |a English. | ||
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Metal oxide semiconductors, Complementary |x Design and construction. | |
| 650 | 0 | |a Integrated circuits |x Design and construction. | |
| 650 | 6 | |a Circuits intégrés |x Conception et construction. | |
| 650 | 7 | |a COMPUTERS |x Machine Theory. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Computer Engineering. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Hardware |x General. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Design and construction |2 fast | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary |x Design and construction |2 fast | |
| 650 | 7 | |a CMOS-Schaltung |2 gnd | |
| 650 | 7 | |a Nanotechnologie |2 gnd | |
| 650 | 7 | |a Layout |g Mikroelektronik |2 gnd | |
| 650 | 7 | |a MOS complémentaires |x Conception et construction. |2 ram | |
| 650 | 7 | |a Circuits intégrés. |2 ram | |
| 650 | 7 | |a Circuit intégré |2 rasuqam | |
| 650 | 7 | |a CMOS (Circuit intégré) |2 rasuqam | |
| 650 | 7 | |a Conception technique. |2 rasuqam | |
| 650 | 7 | |a Nanotechnologie. |2 rasuqam | |
| 653 | |a Electrical and Electronics Engineering. | ||
| 700 | 1 | |a Wong, Ban P., |d 1953- |1 https://id.oclc.org/worldcat/entity/E39PCjKcwwPR8ykmxhFfjChgyq | |
| 758 | |i has work: |a NanoOS circuit and physical design (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGqYc9rFWkXDkgdpDTgTjK |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |t Nano-CMOS circuit and physical design. |d Hoboken, N.J. : John Wiley, ©2005 |w (DLC) 2004002212 |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=227403 |z Texto completo |
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