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Modern receiver front-ends : systems, circuits, and integration /
Architectures BABAK MATINPOUR and JOY LASKAR* Describes the actual implementation of receiver architectures from the initial design to an IC-based product* Presents many tricks-of-the-trade not usually covered in textbooks* Covers a range of practical issues including semiconductor technology select...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
[Hoboken, N.J.] :
Wiley-Interscience,
©2004.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 049 | |a UAMI | ||
| 100 | 1 | |a Laskar, Joy. | |
| 245 | 1 | 0 | |a Modern receiver front-ends : |b systems, circuits, and integration / |c Joy Laskar, Babak Matinpour, Sudipto Chakraborty. |
| 260 | |a [Hoboken, N.J.] : |b Wiley-Interscience, |c ©2004. | ||
| 300 | |a 1 online resource (xiii, 221 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a data file | ||
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a MODERN RECEIVER FRONT-ENDS; CONTENTS; Preface; Acknowledgments; 1 INTRODUCTION; 1.1 Current State of the Art; 2 RECEIVER SYSTEM DESIGN; 2.1 Frequency Planning; 2.1.1 Blockers; 2.1.2 Spurs and Desensing; 2.1.3 Transmitter Leakage; 2.1.4 LO Leakage and Interference; 2.1.5 Image; 2.1.6 Half IF; 2.2 Link Budget Analysis; 2.2.1 Linearity; 2.2.2 Noise; 2.2.3 Signal-to-Noise Ratio; 2.2.4 Receiver Gain; 2.3 Propagation Effects; 2.3.1 Path Loss; 2.3.2 Multipath and Fading; 2.3.3 Equalization; 2.3.4 Diversity; 2.3.5 Coding; 2.4 Interface Planning; 2.5 Conclusion; 3 REVIEW OF RECEIVER ARCHITECTURES | |
| 505 | 8 | |a 3.1 Heterodyne Receivers3.2 Image Reject Receivers; 3.2.1 Hartley Architecture; 3.2.2 Weaver Architecture; 3.3 Zero IF Receivers; 3.4 Low IF Receivers; 3.5 Issues in Direct Conversion Receivers; 3.5.1 Noise; 3.5.2 LO Leakage and Radiation; 3.5.3 Phase and Amplitude Imbalance; 3.5.4 DC Offset; 3.5.5 Intermodulations; 3.6 Architecture Comparison and Trade-off; 3.7 Conclusion; 4 SILICON-BASED RECEIVER DESIGN; 4.1 Receiver Architecture and Design; 4.1.1 System Description and Calculations; 4.1.2 Basics of OFDM; 4.1.3 System Architectures; 4.1.4 System Calculations; 4.2 Circuit Design | |
| 505 | 8 | |a 4.2.1 SiGe BiCMOS Process Technology4.2.2 LNA; 4.2.3 Mixer; 4.2.4 Frequency Divider; 4.3 Receiver Design Steps; 4.3.1 Design and Integration of Building Blocks; 4.3.2 DC Conditions; 4.3.3 Scattering Parameters; 4.3.4 Small-Signal Performance; 4.3.5 Transient Performance; 4.3.6 Noise Performance; 4.3.7 Linearity Performance; 4.3.8 Parasitic Effects; 4.3.9 Process Variation; 4.3.10 50-W and Non-50-W Receivers; 4.4 Layout Considerations; 4.5 Characterization of Receiver Front-Ends; 4.5.1 DC Test; 4.5.2 Functionality Test; 4.5.3 S-Parameter Test; 4.5.4 Conversion Gain Test; 4.5.5 Linearity Test | |
| 505 | 8 | |a 4.5.6 Noise Figure Test4.5.7 I/Q Imbalance; 4.5.8 DC Offset; 4.6 Measurement Results and Discussions; 4.6.1 Close Examination of Noise Figure and I/Q Imbalance; 4.6.2 Comments on I/Q Imbalance; 4.7 Conclusion; 5 SUBHARMONIC RECEIVER DESIGNS; 5.1 Illustration of Subharmonic Techniques; 5.2 Mixing Using Antisymmetric I-V Characteristics; 5.3 Impact of Mismatch Effects; 5.4 DC Offset Cancellation Mechanisms; 5.4.1 Intrinsic DC Offset Cancellation; 5.4.2 Extrinsic DC Offset Cancellation; 5.5 Experimental Verification of DC Offset; 5.6 Waveform Shaping Before Mixing; 5.6.1 Theory and Analysis | |
| 505 | 8 | |a 5.6.2 Experimental Verification on GaAs MESFET APDP5.6.3 Implementation in Silicon; 5.7 Design Steps for APDP-Based Receivers; 5.8 Architectural Illustration; 5.9 Fully Monolithic Receiver Design Using Passive APDP Cores; 5.9.1 Integrated Direct Conversion Receiver MMIC's; 5.9.2 Receiver Blocks; 5.9.3 Additional Receiver Blocks; 5.10 Reconfigurable Multiband Subharmonic Front-Ends; 5.11 Conclusion; 6 ACTIVE SUBHARMONIC RECEIVER DESIGNS; 6.1 Stacking of Switching Cores; 6.1.1 Description and Principles; 6.1.2 Subharmonic Receiver Architecture; 6.2 Parallel Transistor Stacks; 6.2.1 Active Mixer | |
| 520 | |a Architectures BABAK MATINPOUR and JOY LASKAR* Describes the actual implementation of receiver architectures from the initial design to an IC-based product* Presents many tricks-of-the-trade not usually covered in textbooks* Covers a range of practical issues including semiconductor technology selection, cost versus performance, yield, packaging, prototype development, testing, and analysis* Discusses architectures that are employed in modern broadband wireless systems. | ||
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Radio frequency integrated circuits. | |
| 650 | 0 | |a Radio |x Receivers and reception |x Design and construction. | |
| 650 | 6 | |a Circuits intégrés à radiofréquence. | |
| 650 | 7 | |a ANTIQUES & COLLECTIBLES |x Radios & Televisions. |2 bisacsh | |
| 650 | 7 | |a Radio frequency integrated circuits |2 fast | |
| 650 | 7 | |a Radio |x Receivers and reception |x Design and construction |2 fast | |
| 650 | 7 | |a Radiomottakere. |2 tekord | |
| 653 | |a Circuit theory and design |a Mobile wireless communications |a Rf / microwave theory and techniques. | ||
| 700 | 1 | |a Matinpour, Babak. | |
| 700 | 1 | |a Chakraborty, Sudipto. | |
| 758 | |i has work: |a Modern receiver front-ends (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGFbTQrKJHVVyrcpv88FYX |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Laskar, Joy. |t Modern receiver front-ends. |d [Hoboken, N.J.] : Wiley-Interscience, ©2004 |z 0471225916 |w (DLC) 2003019188 |w (OCoLC)52942785 |
| 856 | 4 | 0 | |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=176021 |z Texto completo |
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