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VLSI 2010 Annual Symposium Selected papers /
This book intends to serve as a basis for presenting to young and experienced scientists the latest advances in VLSI technology and related areas, and how they can be effectively employed for the design of modern systems. All contributions to the book have been carefully written, focusing on the ped...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , , , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2011.
|
| Edición: | 1st ed. 2011. |
| Colección: | Lecture Notes in Electrical Engineering,
105 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a VLSI 2010 Annual Symposium |h [electronic resource] : |b Selected papers / |c edited by Nikolaos Voros, Amar Mukherjee, Nicolas Sklavos, Konstantinos Masselos, Michael Huebner. |
| 250 | |a 1st ed. 2011. | ||
| 264 | 1 | |a Dordrecht : |b Springer Netherlands : |b Imprint: Springer, |c 2011. | |
| 300 | |a X, 346 p. |b online resource. | ||
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| 490 | 1 | |a Lecture Notes in Electrical Engineering, |x 1876-1119 ; |v 105 | |
| 505 | 0 | |a 1. Intelligent NOC Hotspot Prediction -- 2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model -- 3. Trust Management Through Hardware Means: Design Concerns and Optimizations -- 4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures -- 5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures -- 6. Adaptive Task Migration Policies for Thermal Control in MPSoCs -- 7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning -- 8. A Scalable Bandwidth Aware Architecture for Connected Component Labelling -- 9. The SATURN Approach to SysML-based HW/SW Codesign -- 10. Mapping Embedded Applications on MPSoC - The MNEMEE approach -- 11. The MOSART Mapping Optimisation for Scalable Multi-core ARchiTecture -- 12. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation -- 13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing -- 14. SUT-RNS Forward and Reverse Converters -- 15. Off-Chip SDRAM Access Through Spidergon STNoC -- 16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore -- 17. FPGA Startup through Sequential Partial and Dynamic Reconfiguration -- 18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware -- 19. System Level Design for Embedded Reconfigurable Systems using MORPHEUS Platform -- 20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach. | |
| 520 | |a This book intends to serve as a basis for presenting to young and experienced scientists the latest advances in VLSI technology and related areas, and how they can be effectively employed for the design of modern systems. All contributions to the book have been carefully written, focusing on the pedagogical aspect so as to become a relevant teaching material. Therefore, this book addresses in particular students, postgraduate programmers/engineers or anyone interested in learning about the state-of-the-art technology in: Architecture - Level Design Solutions Embedded System Design Emerging Devices and Nanocomputing Reconfigurable Systems The book attempts to encompass both theory and technology, and both theoretical and practical design aspects. The authors present the latest research results, ideas, developments, and applications in the above areas that directly influence and become influenced by VLSI circuits, systems and design methods to system level design and Systems-on-Chip. The book includes twenty chapters, divided in four parts. Part I, presents Architecture - Level Design Solutions and especially network-on-chip technologies, cryptographic hardware engineering, multi-core architectures and architectures beyond CMOS; Part II, entitled Embedded System Design, presents novel approaches for designing the next generation of embedded systems focusing on MPSoC and multi-core technologies; Part III is devoted to Emerging Devices and Nanocomputing and presents techniques for efficiently designing and simulating memory systems and converters with low power testing techniques, while it also provides the latest technology on digital microfluidic biochips; Finally, Part IV presents state-of-the-art technologies for Reconfigurable Systems based on FPGA technology and multi-grained reconfigurable hardware. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Computer engineering. | |
| 650 | 0 | |a Computer networks . | |
| 650 | 0 | |a Computer hardware description languages. | |
| 650 | 0 | |a Computers. | |
| 650 | 0 | |a Bioinformatics. | |
| 650 | 0 | |a Electronics. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Computer Engineering and Networks. |
| 650 | 2 | 4 | |a Register-Transfer-Level Implementation. |
| 650 | 2 | 4 | |a Hardware Performance and Reliability. |
| 650 | 2 | 4 | |a Computational and Systems Biology. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 700 | 1 | |a Voros, Nikolaos. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Mukherjee, Amar. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Sklavos, Nicolas. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Masselos, Konstantinos. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Huebner, Michael. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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