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VLSI Physical Design: From Graph Partitioning to Timing Closure
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which i...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2011.
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| Edición: | 1st ed. 2011. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 100 | 1 | |a Kahng, Andrew B. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a VLSI Physical Design: From Graph Partitioning to Timing Closure |h [electronic resource] / |c by Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu. |
| 250 | |a 1st ed. 2011. | ||
| 264 | 1 | |a Dordrecht : |b Springer Netherlands : |b Imprint: Springer, |c 2011. | |
| 300 | |a XI, 310 p. |b online resource. | ||
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| 520 | |a Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure. For Slides and Other Information: https://www.ifte.de/books/eda/index.html. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Logic design. | |
| 650 | 0 | |a Electronics. | |
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Logic Design. |
| 650 | 2 | 4 | |a Electronics and Microelectronics, Instrumentation. |
| 650 | 2 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 | 1 | |a Lienig, Jens. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Markov, Igor L. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 700 | 1 | |a Hu, Jin. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9789048195909 |
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| 776 | 0 | 8 | |i Printed edition: |z 9789048195923 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-90-481-9591-6 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
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| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||