SynDEVS Co-Design Flow A Hardware / Software Co-Design Flow Based on the Discrete Event System Specification Model of Computation /

The complexity of modern embedded systems has increased rapidly in the recent past. Introducing models of computation into the design flow has significantly raised the abstraction in system level design of embedded systems. Establishing such high abstraction levels in common hardware /software co-de...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Molter, H. Gregor (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Wiesbaden : Springer Fachmedien Wiesbaden : Imprint: Springer Vieweg, 2012.
Edición:1st ed. 2012.
Temas:
Computer science.
Computer Science.
Acceso en línea:Texto Completo

MARC

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100 1 |a Molter, H. Gregor.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a SynDEVS Co-Design Flow  |h [electronic resource] :  |b A Hardware / Software Co-Design Flow Based on the Discrete Event System Specification Model of Computation /  |c by H. Gregor Molter. 
250 |a 1st ed. 2012. 
264 1 |a Wiesbaden :  |b Springer Fachmedien Wiesbaden :  |b Imprint: Springer Vieweg,  |c 2012. 
300 |a XXVI, 198 p. 57 illus., 45 illus. in color.  |b online resource. 
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505 0 |a Model of Computation -- Discrete Event System Specification -- Hardware / Software Co-Design Flow -- Model Transformation -- Time RepresentationModel Transformation to Hardware and Software. 
520 |a The complexity of modern embedded systems has increased rapidly in the recent past. Introducing models of computation into the design flow has significantly raised the abstraction in system level design of embedded systems. Establishing such high abstraction levels in common hardware /software co-design flows is still in its infancy. H. Gregor Molter develops a hardware / software co-design flow based on the Discrete Event System Specification model of computation. He advocates that such a system level design flow should exploit a timed model of computation to allow a broad application field. The presented design flow will transform timed DEVS models to both synthesizable VHDL source code and embeddable C++ source code.   Target Groups Researchers and students in the fields of abstract system level design and synthesizable models of computation; Practitioners in the fields of cyber physical systems or embedded systems design.   About the Author H. Gregor Molter completed his doctoral thesis at the department of Integrated Circuits and Systems Lab, Technische Universität Darmstadt, under the supervision of Prof. Dr.-Ing. Sorin A. Huss.   Target Groups Researchers and students in the fields of abstract system level design and synthesizable models of computation; Practitioners in the fields of cyber physical systems or embedded systems design.   About the Author H. Gregor Molter completed his doctoral thesis at the department of Integrated Circuits and Systems Lab, Technische Universität Darmstadt, under the supervision of Prof. Dr.-Ing. Sorin A. Huss. 
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776 0 8 |i Printed edition:  |z 9783658003982 
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950 |a Computer Science (SpringerNature-11645) 
950 |a Computer Science (R0) (SpringerNature-43710) 

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