Transactions on High-Performance Embedded Architectures and Compilers IV

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Stenström, Per (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2011.
Edición:1st ed. 2011.
Colección:Transactions on High-Performance Embedded Architectures and Compilers, 6760
Temas:
Computer arithmetic and logic units.
Microprocessors.
Computer architecture.
Computer input-output equipment.
Logic design.
Computer networks .
Compilers (Computer programs).
Arithmetic and Logic Structures.
Processor Architectures.
Input/Output and Data Communications.
Logic Design.
Computer Communication Networks.
Compilers and Interpreters.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors
  • Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces
  • Compiler Directed Issue Queue Energy Reduction
  • A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors
  • Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors
  • Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC)
  • A Highly Scalable Parallel Implementation of H.264
  • Communication Based Proactive Link Power Management
  • Finding Extreme Behaviors in Microprocessor Workloads
  • Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
  • Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms
  • Transaction Reordering to Reduce Aborts in Software Transactional Memory
  • A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture
  • A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM
  • Software Transactional Memory Validation - Time and Space Considerations Tiled Multi-Core Stream Architecture
  • An Efficient and Flexible Task Management for Many Cores
  • Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation
  • On Two-layer Brain-inspired Hierarchical Topologies: A Rent's Rule Approach
  • Advanced Packet Segmentation and Buffering Algorithms in Network Processors
  • Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation
  • A Cost Model for Partial Dynamic Reconfiguration
  • Heterogeneous Design in Functional DIF
  • Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration.

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