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High Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings /
This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were careful...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , , , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Berlin, Heidelberg :
Springer Berlin Heidelberg : Imprint: Springer,
2010.
|
| Edición: | 1st ed. 2010. |
| Colección: | Theoretical Computer Science and General Issues,
5952 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a High Performance Embedded Architectures and Compilers |h [electronic resource] : |b 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / |c edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell. |
| 250 | |a 1st ed. 2010. | ||
| 264 | 1 | |a Berlin, Heidelberg : |b Springer Berlin Heidelberg : |b Imprint: Springer, |c 2010. | |
| 300 | |a XIII, 370 p. |b online resource. | ||
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| 490 | 1 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5952 | |
| 505 | 0 | |a Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload - Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. | |
| 520 | |a This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators. | ||
| 650 | 0 | |a Computer programming. | |
| 650 | 0 | |a Computer arithmetic and logic units. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Computer input-output equipment. | |
| 650 | 0 | |a Logic design. | |
| 650 | 0 | |a Computer networks . | |
| 650 | 1 | 4 | |a Programming Techniques. |
| 650 | 2 | 4 | |a Arithmetic and Logic Structures. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 650 | 2 | 4 | |a Input/Output and Data Communications. |
| 650 | 2 | 4 | |a Logic Design. |
| 650 | 2 | 4 | |a Computer Communication Networks. |
| 700 | 1 | |a Patt, Yale N. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Foglia, Pierfrancesco. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Duesterwald, Evelyn. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Faraboschi, Paolo. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Martorell, Xavier. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9783642115165 |
| 776 | 0 | 8 | |i Printed edition: |z 9783642115141 |
| 830 | 0 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5952 | |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-3-642-11515-8 |z Texto Completo |
| 912 | |a ZDB-2-SCS | ||
| 912 | |a ZDB-2-SXCS | ||
| 912 | |a ZDB-2-LNC | ||
| 950 | |a Computer Science (SpringerNature-11645) | ||
| 950 | |a Computer Science (R0) (SpringerNature-43710) | ||